Serial Management Controllers (SMCs)
MC68360 USER’S MANUAL
REN—SMC Receive Enable
0 = SMC receiver disabled
1 = SMC receiver enabled
7.11.14.5 SMC MONITOR CHANNEL RX BD. The CP reports information about the moni-
tor channel receive byte using this BD.
E—Empty
0 = This bit is cleared by the CP to indicate that data byte associated with this BD is
now available to the CPU32+ core.
1 = This bit is set by the CPU32+ core to indicate that the data byte associated with
this BD has been read.
When the SMC implements the monitor channel protocol, the SMC will wait until this bit
is set by the CPU32+ core before acknowledging the monitor channel data. In the trans-
parent mode, additional received data bytes will be discarded until the E-bit is set by the
CPU32+ core.
L—Last (EOM)
This bit is valid only when the SMC implements the monitor channel protocol. This bit is
set when the end-of-message (EOM) indication is received on the E-bit.
NOTE
When this bit is set, the data byte is not valid.
ER—Error Condition
This bit is valid only when the SMC implements the monitor channel protocol. This bit is
set when an error condition occurs on the monitor channel protocol. (A new byte is trans-
mitted before the SMC acknowledges the previous byte.)
MS—Data Mismatch
This bit is valid only when the SMC implements the monitor channel protocol. This bit is
set when two different consecutive bytes are received and is cleared when the last two
consecutive bytes match. The SMC waits for the reception of two identical consecutive
bytes before writing new data to the Rx BD.
Bits 11–10—Reserved
These bits should be cleared by the user.
DATA—Data Field
The data field contains the monitor channel data byte received by the SMC.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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