CPU32+
MC68360 USER’S MANUAL
5.3.3.1 CONDITION CODE REGISTER. The CCR portion of the SR contains five bits that
indicate the result of a processor operation.
Table 5-2 lists the effect of each instruction on
these bits. The carry bit and the multiprecision extend bit are separate in the M68000 Family
to simplify programming techniques that use them. Refer to
Table 5-3 as an example.
Table 5-2. Instruction Set Summary (Concluded)
Opcode
Operation
Syntax
RTS
(SP)
PC; SP + 4 SP
RTS
SBCD
Destination10 – Source10 – X Destination
SBCD Dx,Dy
SBCD –(Ax),–(Ay)
Scc
If Condition True
then 1s
Destination
else 0s
Destination
Scc
ea
STOP
If supervisor state
then Immediate Data
SR; STOP
else TRAP
STOP #
data
SUB
Destination – Source
Destination
SUB
ea,Dn
SUB Dn,
ea
SUBA
Destination – Source
Destination
SUBA
ea,An
SUBI
Destination – Immediate Data
Destination
SUBI #
data,ea
SUBQ
Destination – Immediate Data
Destination
SUBQ #
data,ea
SUBX
Destination – Source – X
Destination
SUBX Dx,Dy
SUBX –(Ax),–(Ay)
SWAP
Register [31:16]
Register [15:0]
SWAP Dn
TAS
Destination Tested
Condition Codes;
1
bit 7 of Destination
TAS
ea
TBLS
ENTRY(n) + {(ENTRY(n + 1) – ENTRY(n))
× Dx[7:0]} /
256
Dx
TBLS.
size ea, Dx
TBLS.
size Dym:Dyn, Dx
TBLSN
ENTRY(n)
× 256 + {(ENTRY(n + 1) – ENTRY(n)) × Dx
[7:0]}
Dx
TBLSN.
size ea,Dx
TBLSN.
size Dym:Dyn, Dx
TBLU
ENTRY(n) + {(ENTRY(n + 1) – ENTRY(n))
× Dx[7:0]} /
256
Dx
TBLU.
size ea,Dx
TBLU.
size Dym:Dyn, Dx
TBLUN
ENTRY(n)
× 256 + {(ENTRY(n + 1) – ENTRY(n)) ×
Dx[7:0]}
Dx
TBLUN.
size ea,Dx
TBLUN.
size Dym:Dyn,Dx
TRAP
SSP – 2
SSP; Format/Offset (SSP);
SSP – 4
SSP; PC (SSP); SSP – 2 SSP;
SR
(SSP); Vector Address PC
TRAP #
vector
TRAPcc
If cc then TRAP
TRAPcc
TRAPcc.W #
data
TRAPcc.L
#data
TRAPV
If V then TRAP
TRAPV
TST
Destination Tested
Condition Codes
TST
ea
UNLK
An
SP; (SP) An; SP + 4 SP
UNLK An
NOTE 1: d is direction, L or R.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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