MC68360 USER’S MANUAL
APPENDIX D
MC68MH360 PRODUCT BRIEF
The MC68MH360 is a derivative of the MC68360 QUICC.
It is also known as the
QUICC32.
The QUICC32 has some modifications in the Communication Processor Module (CPM)
hardware and a larger internal dual port RAM. These hardware changes in combination with
a new ROM based microcode, called QMC (QUICC Multichannel Controller), emulates up
to 32 HDLC channels within one SCC. The MH360 is ideal in primary rate ISDN applications
and interfaces directly to a E1/T1 line and is capable of terminating all time slots using HDLC
or transparent mode of operation. One of the time slot assigners (SI) is dedicated to the use
of the QMC. The SI transfers the whole frame or selected time slots to one SCC. All other
features remain unchanged and the QUICC32 is pin compatible with the other family mem-
bers.
A QUICC32 in non-QMC mode has exactly the same functionality as a standard MC68360
with the exception that the Centronics and BISYNC protocols have been removed on the
QUICC32 to create ROM space for the QMC protocol.
D.1 QUICC32 KEY FEATURES
The following list summarizes the key MC68MH360 QUICC32 features:
D.1.1 General
Up to 32 Independent Communication Channels
Arbitrary Mapping of Any of 0-31 Channels to Any of 0-31 TDM Time Slots
Can Support Arbitrary Mapping of Any of 0-31 Channels to Any of 0-63 TDM Time Slots
in Case of Common Rx & Tx Mapping
Independent Mapping for Receive/Transmit
Supports Either QUICC Transparent or QUICC HDLC Protocols for Each Channel
QUICC-Like Manner for Channel Programming and Parameter Passing
Up to 64 DMA Channels with Linear Buffer Array
Interrupt Circular Buffer with Programmable Size and Overflow Identification
Global Loop Mode
Individual Channel Loop Mode
Programmable Frame Length (Via QUICC’s SI)
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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