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参数资料
| 型号： | MC68HC05RC9P |
| 厂商： | MOTOROLA INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP28 |
| 封装： | PLASTIC, DIP-28 |
| 文件页数： | 71/124页 |
| 文件大小： | 457K |
| 代理商： | MC68HC05RC9P |
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NON-DISCLOSURE
AGREEMENT
REQUIRED
Resets
General Release Specification
MC68HC05RC18 — Rev. 2.0
50
Resets
MOTOROLA
5.4 Low-Power External Reset (LPRST)
This pin is connected to a Schmitt trigger input gate to provide an upper
and lower threshold voltage separated by a minimum amount of
hysteresis. The LPRST pin is one of the two external sources of a reset.
This external reset occurs whenever the LPRST pin is pulled below the
lower threshold and remains in reset until the LPRST pin rises above the
upper threshold. This active-low input will, in addition to generating the
RST signal and resetting the CPU and peripherals, halt all internal
processor clocks and the crystal oscillator. The MCU will remain in this
low-power reset condition as long as a logic 0 remains on LPRST. When
a logic 1 is applied to LPRST, processor clocks will be re-enabled with
the MCU remaining in reset until the 4064 internal processor clock cycle
(tcyc) oscillator stabilization delay is completed. If any other reset
function is active at the end of this 4064-cycle delay, the RST signal
remains in the reset condition until the other reset condition(s) end.
5.5 Internal Resets
The three internally generated resets are the initial power-on reset
function, the COP watchdog timer reset, and the illegal address detector.
Termination of the external RESET input or the internal COP watchdog
timer are the only reset sources that can place the MCU into a non-user
operating mode. POR and LPRST place the MCU in user mode while the
illegal address reset has no effect on operating mode.
5.5.1 Power-On Reset (POR)
The internal POR is generated on power-up to allow the clock oscillator
to stabilize. The POR is strictly for power turn-on conditions and is not
able to detect a drop in the power supply voltage (brown-out). There is
an oscillator stabilization delay of 4064 internal processor bus clock
cycles (PH2) after the oscillator becomes active.
The POR generates the RST signal that resets the CPU. If any other
reset function is active at the end of this 4064-cycle delay, the RST
signal remains in the reset condition until the other reset condition(s)
ends.
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