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参数资料
| 型号： | MC68HC05RC9P |
| 厂商： | MOTOROLA INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP28 |
| 封装： | PLASTIC, DIP-28 |
| 文件页数： | 72/124页 |
| 文件大小： | 457K |
| 代理商： | MC68HC05RC9P |
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Resets
Internal Resets
MC68HC05RC18 — Rev. 2.0
General Release Specification
MOTOROLA
Resets
51
NON-DISCLOSURE
AGREEMENT
REQUIRED
CAUTION:
The VDD voltage should rise sufficiently fast to reach the minimum
operating voltage for the given oscillator frequency before the 4064-
cycle internal processor clock timeout period expires. If VDD rises too
slowly, then either the RESET or LPRST pin should be driven low (less
than VIL) until VDD reaches the minimum operating level for the oscillator
frequency.
5.5.2 Computer Operating Properly Reset (COPR)
The MCU contains a watchdog timer that automatically times out if not
reset (cleared) within a specific time by a program reset sequence. If the
COP watchdog timer is allowed to timeout, an internal reset is generated
to reset the MCU.
The COP reset function is enabled or disabled by a mask option and is
verified during production testing.
5.5.2.1 Resetting the COP
Writing a zero to the COPF bit prevents a COP reset. This action resets
the counter and begins the timeout period again. The COPF bit is bit 0
of address $3FF0. A read of address $3FF0 returns user data
programmed at that location.
5.5.2.2 COP During Wait Mode
The COP continues to operate normally during wait mode. The software
should pull the device out of wait mode periodically and reset the COP
by writing to the COPF bit to prevent a COP reset.
5.5.2.3 COP During Stop Mode
When STOP is executed, the COP counter will be cleared and held in
that state until the STOP state is exited. This is true whether STOP is
enabled and the chip enters an actual STOP state (when all clocks are
stopped) or if STOP is disabled and only the internal PH1 and PH2 are
stopped (a wait-like state). If a reset is used to exit stop mode, the COP
counter is held in reset until 4064 POR cycles are completed, at which
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