- 您现在的位置：买卖IC网 > PDF目录45226 > MC68HC11C0FN3 (MOTOROLA INC) 8-BIT, 3 MHz, MICROCONTROLLER, PQCC68 PDF资料下载
参数资料
| 型号： | MC68HC11C0FN3 |
| 厂商： | MOTOROLA INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, 3 MHz, MICROCONTROLLER, PQCC68 |
| 封装： | PLASTIC, LCC-68 |
| 文件页数： | 10/76页 |
| 文件大小： | 394K |
| 代理商： | MC68HC11C0FN3 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页当前第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页
MOTOROLA
MC68HC11C0
18
MC68HC11C0TS/D
4 Memory Expansion and Chip Selects
The MC68HC11C0 has the ability to extend the addressing range of the M68HC11 CPU beyond the
physical 64-Kbyte limit of the 16 CPU address lines. The extra addressing capability is provided by a
register-based paging scheme using two expansion address lines and the physical 64 Kbytes of CPU
address space.
Two additional on-chip blocks are necessary to support extended addressing. The first block imple-
ments additional address lines that become active only when required by the CPU. The second block
provides chip-select signals that simplify the interface to external peripheral devices. Both of these
blocks are fully programmable by values written to associated control registers.
4.1 Memory Expansion
Memory expansion is achieved by manipulating the CPU address lines such that, even though the CPU
cannot distinguish more than 64 Kbytes of physical memory, up to 256 Kbytes can be accessed through
a paged memory scheme. Additional address lines XA[17:16] are provided to allow banks of expanded
memory to be selected to appear in a specified bank window. XA[17:16] are implemented as alternate
functions of port G pins PG[2:1]. Bits in the port G enable register (PGEN) define which port G pins are
used for chip selects and memory expansion address lines and which are used for general-purpose I/
O. Port G pull-ups are enabled out of reset in order to provide a logic level one on all chip select and
memory expansion address lines.
The MEM[1:0] bits in PGEN select one of the three memory expansion modes. XA[17:10] in MXHADR/
MXLADR contain the expansion address offset with respect to the current CPU address. When memory
expansion is enabled, and the CPU address falls within the memory expansion window defined by val-
ues in PGxADR registers, CSPROG is activated and the CPU address ADDR[15:0] will be added to the
value in MXHADR/MXLADR and possibly extended to include XA[17:16] before being driven out to the
external device. XA[17:16] will be used only if addressing is extended beyond 64 Kbytes. If the CPU
address falls outside the expansion window, ADDR[15:10] simply reflect the internal CPU address. AD-
DR[9:0] always reflect the internal CPU address. Refer to the Memory Expansion and Program Chip
Select Block Diagram.
In 64-Kbyte mode with no expansion, addressing is limited to 64 Kbytes and ADDR[15:10] are used to
decode the chip selects. Chip select granularity is 1 Kbyte. Memory expansion is disabled. The pro-
gram/vector chip select is disabled. ADDR[15:10] reflect the internal CPU address signals.
In 64-Kbyte expansion mode, addressing is limited to 64 Kbytes and ADDR[15:10] are used to decode
the chip selects. CPU address ADDR[15:10] are recalculated based on the value in MXHADR/MXLADR
registers before being driven out on ADDR[15:10] pins. The program chip select is active if the CPU
address falls within the chip select range defined by values in PGxADR registers. If the CPU address
falls outside the chip select window, ADDR[15:10] remain unchanged and simply reflect the internal ad-
dress signals. XA[17:16] are general-purpose I/O. ADDR[9:0] always reflect the CPU address signals.
In 128-Kbyte expansion mode, ADDR[15:10] are used to decode the chip selects. If the CPU address
falls within the chip select range defined by values in PGxADR registers, it is activated and CPU address
ADDR[15:10] are recalculated based on the value in MXHADR/MXLADR registers before being driven
out on XA16 and ADDR[15:10] pins. If the CPU address falls outside the chip select window, AD-
DR[15:10] simply reflect the internal address signals. XA16 reflects the state of the XA16 bit in MX-
HADR. XA17 is general-purpose I/O. ADDR[9:0] always reflect the CPU address.
In 256-Kbyte expansion mode, ADDR[15:10] are used to decode the chip selects. If the CPU address
falls within the chip select range defined by values in PGxADR registers, it is activated and CPU address
ADDR[15:10] are recalculated based on the value in MXHADR/MXLADR registers before being driven
out on XA[17:16] and ADDR[15:10] pins. If the CPU address falls outside the chip select window, AD-
DR[15:10] simply reflect the internal address signals. XA[17:16] reflect the state of the XA[17:16] bits in
MXHADR/MXLADR. ADDR[9:0] always reflect the CPU address.
相关PDF资料 |
PDF描述 |
|---|---|
| MC68HC11D0CFN2 | 8-BIT, 2 MHz, MICROCONTROLLER, PQCC44 |
| MC68HC11D0CFB2 | 8-BIT, 2 MHz, MICROCONTROLLER, PQFP44 |
| MC68HC11D3CFN2 | 8-BIT, MROM, 2 MHz, MICROCONTROLLER, PQCC44 |
| MC68HC711D3CP3 | 8-BIT, OTPROM, 3 MHz, MICROCONTROLLER, PDIP40 |
| MC68HC11D3CFN3 | 8-BIT, MROM, 3 MHz, MICROCONTROLLER, PQCC44 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| MC68HC11C0FU3 | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:8-Bit Microcontroller |
| MC68HC11C0MFN2 | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:8-Bit Microcontroller |
| MC68HC11C0MFU2 | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:8-Bit Microcontroller |
| MC68HC11C0VFN2 | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:8-Bit Microcontroller |
| MC68HC11C0VFU2 | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:8-Bit Microcontroller |
发布紧急采购，3分钟左右您将得到回复。