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参数资料
| 型号： | MC68HC11C0FN3 |
| 厂商： | MOTOROLA INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, 3 MHz, MICROCONTROLLER, PQCC68 |
| 封装： | PLASTIC, LCC-68 |
| 文件页数： | 57/76页 |
| 文件大小： | 394K |
| 代理商： | MC68HC11C0FN3 |
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MOTOROLA
MC68HC11C0
60
MC68HC11C0TS/D
and share the PD1 pin. If an open-drain type driver is used for the TxD output, RxD and TxD can still
be externally wire-OR configured. The open-drain control in DIOCTL allows either full CMOS driving or
open-drain driving on the TxD output. Refer to the DIOCTL description.
The SCI system external pins are implemented as an alternate function of port D pins. In addition to the
port D data direction register (DDRD), the port D I/O control register (DIOCTL) determines which func-
tions are performed by port D pins. The port D open drain mode (DODM) register controls the driver
type for each port D pin configured as an output. Refer to the descriptions of PORTD, DDRD, DIOCTL,
and DODM registers.
The bits in three control registers and one status register control operation of the SCI. The SCI control
registers (SCCR1 and SCCR2) are used to configure the SCI and to enable certain features. The baud
rate control register (BAUD) selects the SCI prescaler and baud rate. Bits in the SCI status register (SC-
SR) flag certain occurrences and control the SCI system accordingly. If enabled by bits in SCCR2, some
SCI status bits in SCSR can generate interrupt requests. Interrupt-generating flag bits in SCSR are
cleared automatically when the CPU services the SCI request. Refer to the descriptions of SCCR1,
SCCR2, BAUD, and SCSR.
The SCI data register (SCDR) is comprised of two separate registers — the receive data register and
the transmit data register. When SCDR is read, the receive data register is accessed. When SCDR is
written, the transmit data register is accessed. If nine-bit data format is used, R8 and T8 bits in SCCR1
contain the ninth receive data bit and the ninth transmit data bit, respectively. Both the transmit and re-
ceive data registers are coupled to serial shift registers. When data to be transmitted is written to SCDR
the data is shifted from the transmit data register to the serial shift register in a parallel fashion. The
contents of the shift register are then transmitted serially out the TxD pin. When serial data is received
on the RxD pin, it enters the serial shift register. When the shift register is full, the entire contents are
shifted in parallel to the SCDR register. The size of the shift register changes automatically according
to the state of the M bit in SCCR1. However, if nine-bit data is selected it is necessary to read or write
the ninth data bit (R8 or T8) in SCCR1 first to ensure that the contents of the shift register are correct.
Refer to the block diagrams for the SCI receiver, SCI transmitter, and baud rate generator.
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| MC68HC11C0FU3 | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:8-Bit Microcontroller |
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