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参数资料
| 型号： | MC68HC11C0FN3 |
| 厂商： | MOTOROLA INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, 3 MHz, MICROCONTROLLER, PQCC68 |
| 封装： | PLASTIC, LCC-68 |
| 文件页数： | 75/76页 |
| 文件大小： | 394K |
| 代理商： | MC68HC11C0FN3 |
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MOTOROLA
MC68HC11C0
8
MC68HC11C0TS/D
RAMON — RAM Enable
Refer to 3 On-Chip Memory.
Bit 0 — Not implemented
Always reads zero
Figure 4 Address/Data Demultiplexing
2.2 Single-Chip Mode
In single-chip operating mode, the MC68HC11C0 is a stand-alone microcontroller with no external ad-
dress or data bus. External address and data lines are disabled. Bootloader ROM appears in the mem-
ory map at locations $BC00–$BFFF and $FC00–$FFFF. Since there is no external address or data bus,
the user must make certain that the RAM contains valid code before entering single-chip mode. The
register block is initially located at $0000 and can be remapped to any 1-Kbyte boundary. RAM is initially
located at $0400–$04FF and can be remapped to any 1-Kbyte boundary. Vectors are fetched internally
from locations $FFC0–$FFFF. Refer to the memory map diagram.
2.3 Bootstrap Mode
Bootstrap mode allows special-purpose programs to be entered into internal RAM. This mode is entered
by resetting to special test mode and then clearing the MDA bit in HPRIO register. When this mode is
selected, a 1024-byte bootstrap ROM becomes present in the memory map. Reset and interrupt vectors
ADDR15
ADDR14
ADDR13
ADDR12
ADDR11
ADDR10
ADDR9
ADDR8
ADDR7/DATA7
ADDR6/DATA6
ADDR5/DATA5
ADDR4/DATA4
ADDR3/DATA3
ADDR2/DATA2
ADDR1/DATA1
ADDR0/DATA0
DATA1
DATA2
DATA3
DATA4
DATA5
DATA6
DATA7
DATA8
LE
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q0
ADDR7
ADDR6
ADDR5
ADDR4
ADDR3
ADDR2
ADDR1
ADDR0
R/W/WR
E/RD
WE
ADDR15
ADDR14
ADDR13
ADDR12
ADDR11
ADDR10
ADDR9
ADDR8
MC54/74HC373
DATA7
DATA6
DATA5
DATA4
DATA3
DATA2
DATA1
DATA0
AS
MC68HC11C0
NOTE: Use of the RD and
WR signals instead of E and
R/W will eliminate the need
for the external inverters and
NAND gate.
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相关代理商/技术参数 |
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| MC68HC11C0FU3 | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:8-Bit Microcontroller |
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