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| 型号： | MAX8745ETJ+T |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 32/36页 |
| 文件大小： | 0K |
| 描述： | IC CNTRLR PWR SUP QUAD 32TQFN |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| 应用： | 控制器，笔记本电脑电源系统 |
| 输入电压： | 6 V ~ 26 V |
| 输出数： | 4 |
| 输出电压： | 3.3V，5V，1 V ~ 26 V |
| 工作温度： | 0°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-WFQFN 裸露焊盘 |
| 供应商设备封装： | 32-TQFN-EP（5x5） |
| 包装： | 带卷 (TR) |
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High-Efficiency, Quad-Output, Main Power-
Supply Controllers for Notebook Computers
(V GS = 5V). Using the above equation, the required
boost capacitance would be:
the transistor’s package and mounting must exceed the
actual power dissipation in the device. The power dissi-
pation equals the maximum load current times the max-
C BST =
13 nC
200 mV
= 0 . 065 μF
imum input-to-output differential:
PWR = I LOAD(MAX) (V INA -V OUTA )
R 5 = R 6 ? OUTA ? 1 ?
A V ( LDO ) = ?
? ? 1 + I
? V T ? ?
LOAD ?
I LOAD ( MAX ) = ? I DRV ? V BE ? β MIN
Selecting the closest standard value, this example
requires a 0.1μF ceramic capacitor.
LDOA Design Procedure
Output Voltage Selection
Adjust the auxiliary linear regulator’s output voltage by
connecting a resistive divider between OUTA and ana-
log ground with the center tap connected to FBA
(Figure 1). Select R6 in the 10k Ω to 30k Ω range, and
calculate R5 with the following equation:
? V ?
? V FBA ?
where V FBA = 1.0V.
Transistor Selection
The pass transistor must meet specifications for current
gain ( β ), input capacitance, collector-emitter saturation
voltage, and power dissipation. The transistor’s current
gain limits the guaranteed maximum output current to:
? ?
? R BE ?
where I DRV is the minimum guaranteed base drive cur-
rent, V BE is the base-to-emitter voltage of the transistor,
and R BE is the pullup resistor connected between the
transistor’s base and emitter. Furthermore, the transis-
PWR = I LOAD(MAX) V CE
LDOA Stability Requirements
The MAX8744/MAX8745 linear-regulator controller uses
an internal transconductance amplifier to drive an exter-
nal pnp pass transistor. The transconductance amplifier,
the pass transistor, the base-to-emitter resistor, and the
output capacitor determine the loop stability.
The transconductance amplifier regulates the output
voltage by controlling the pass transistor’s base cur-
rent. The total DC loop gain is approximately:
? 5 . 5 V ? ? I BIAS h FE ?
?
where V T is 26mV at room temperature, h FE is the pass
transistor’s DC gain, and I BIAS is the current through
the base-to-emitter resistor (R BE ). The 680 Ω base-to-
emitter resistor used in Figure 1 was chosen to provide
a 1mA bias current (I BIAS ).
The output capacitor and the load resistance create the
dominant pole in the system. However, the internal ampli-
fier delay, the pass transistor’s input capacitance, and the
stray capacitance at the feedback node create additional
poles in the system, and the output capacitor’s ESR gen-
erates a zero. For proper operation, use the following
steps to ensure the linear-regulator stability:
1) First, calculate the dominant pole set by the linear
regulator’s output capacitor and the load resistor:
tor’s current gain increases the linear regulator’s DC
loop gain (see the LDOA Stability Requirements sec-
tion), so excessive gain destabilizes the output.
Therefore, transistors with current gain over 100 at the
f POLE ( LDO ) =
1
2 π C OUTA R LOAD
maximum output current can be difficult to stabilize and
are not recommended. The transistor’s input capaci-
tance and input resistance also create a second pole,
which could be low enough to make the output unsta-
ble when heavily loaded.
The transistor’s saturation voltage at the maximum out-
put current determines the minimum input-to-output
voltage differential that the linear regulator supports.
Alternatively, the package’s power dissipation could
limit the useable maximum input-to-output voltage dif-
ferential. The maximum power dissipation capability of
where C OUTA is the output capacitance of the aux-
iliary LDO and R LOAD is the load resistance corre-
sponding to the maximum load current. The unity-
gain crossover of the linear regulator is:
f CROSSOVER = A V(LDO) f POLE(LDO)
2) The pole caused by the internal amplifier delay is at
approximately 1MHz:
f POLE(AMP) ≈ 1MHz
32
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