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| 型号： | MAX8745ETJ+T |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 33/36页 |
| 文件大小： | 0K |
| 描述： | IC CNTRLR PWR SUP QUAD 32TQFN |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| 应用： | 控制器，笔记本电脑电源系统 |
| 输入电压： | 6 V ~ 26 V |
| 输出数： | 4 |
| 输出电压： | 3.3V，5V，1 V ~ 26 V |
| 工作温度： | 0°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-WFQFN 裸露焊盘 |
| 供应商设备封装： | 32-TQFN-EP（5x5） |
| 包装： | 带卷 (TR) |
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High-Efficiency, Quad-Output, Main Power-
Supply Controllers for Notebook Computers
f POLE ( CIN ) ≈
3) Next, calculate the pole set by the transistor’s input
capacitance, the transistor’s input resistance, and the
base-to-emitter pullup resistor. Since the transistor’s
input resistance (h FE /g m ) is typically much greater
than the base-to-emitter pullup resistance, the pole
can be determined from the simplified equation:
1
2 π C IN R IN
high gate capacitance of the p-channel MOSFET
lowers the f POLE(CIN) and can cause instability. A
large output capacitance must be used to reduce
the unity-gain bandwidth and ensure that the pole
is well above the unity-gain crossover frequency.
Applications Information
Duty-Cycle Limits
C IN =
g m
2 π f T
Minimum Input Voltage
The minimum input operating voltage (dropout voltage) is
restricted by the maximum duty-cycle specification (see
f POLE ( CIN ) ≈ T
f POLE ( FBA ) =
? 1 ? ( V OUT + V DIS )
V IN ( MIN ) = V OUT + V CHG + h ?
where g m is the transconductance of the pass tran-
sistor, and f T is the transition frequency. Both para-
meters can be found in the transistor’s data sheet.
Therefore, the equation can be further reduced to:
f
h FE
4) Next, calculate the pole set by the linear regulator’s
feedback resistance and the capacitance between
FBA and ground (approximately 5pF including
stray capacitance):
1
2 π C FBA ( R 5 || R 6 )
5) Next, calculate the zero caused by the output
the Electrical Characteristics table). For the best dropout
performance, use the slowest switching frequency set-
ting (200kHz, FSEL = GND). However, keep in mind that
the transient performance gets worse as the step-down
regulators approach the dropout voltage, so bulk output
capacitance must be added (see the voltage sag and
soar equations in the Transient Response section of the
SMPS Design Procedure section). The absolute point of
dropout occurs when the inductor current ramps down
during the off-time ( Δ I DOWN ) as much as it ramps up
during the on-time ( Δ I UP ). This results in a minimum oper-
ating voltage defined by the following equation:
? 1 ?
? D MAX ?
capacitor’s ESR:
f ZERO ( ESR ) =
1
2 π C OUTA R ESR
where V CHG and V DIS are the parasitic voltage drops in
the charge and discharge paths, respectively. A rea-
sonable minimum value for h is 1.5, while the absolute
V IN ( SKIP ) = V OUT ? ?
? f OSC ON ( MIN ) ?
where R ESR is the equivalent series resistance of
C OUTA .
6) To ensure stability, choose C OUTA large enough so
that the crossover occurs well before the poles and
zero calculated in steps 2 through 5. The poles in
steps 3 and 4 generally occur at several MHz, and
using ceramic output capacitors ensures the ESR
zero occurs at several MHz as well. Placing the
crossover frequency below 500kHz is typically suf-
ficient to avoid the amplifier delay pole and gener-
ally works well, unless unusual component
selection or extra capacitance moves the other
poles or zero below 1MHz.
A capacitor connected between the linear regula-
tor’s output and the feedback node can improve
the transient response and reduce the noise cou-
pled into the feedback loop.
If a low-dropout solution is required, an external p-
channel MOSFET pass transistor could be used.
However, a pMOS-based linear regulator requires
higher output capacitance to stabilize the loop. The
minimum input voltage is calculated with h = 1.
Maximum Input Voltage
The MAX8744/MAX8745 controllers include a minimum
on-time specification, which determines the maximum
input operating voltage that maintains the selected
switching frequency (see the Electrical Characteristics
table). Operation above this maximum input voltage
results in pulse-skipping operation, regardless of the
operating mode selected by SKIP . At the beginning of
each cycle, if the output voltage is still above the feed-
back threshold voltage, the controller does not trigger
an on-time pulse, effectively skipping a cycle. This
allows the controller to maintain regulation above the
maximum input voltage, but forces the controller to
effectively operate with a lower switching frequency.
This results in an input threshold voltage at which the
controller begins to skip pulses (V IN(SKIP) ):
? 1 ?
t
where f OSC is the switching frequency selected by FSEL.
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