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| 型号： | MAX8745ETJ+T |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 34/36页 |
| 文件大小： | 0K |
| 描述： | IC CNTRLR PWR SUP QUAD 32TQFN |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| 应用： | 控制器，笔记本电脑电源系统 |
| 输入电压： | 6 V ~ 26 V |
| 输出数： | 4 |
| 输出电压： | 3.3V，5V，1 V ~ 26 V |
| 工作温度： | 0°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-WFQFN 裸露焊盘 |
| 供应商设备封装： | 32-TQFN-EP（5x5） |
| 包装： | 带卷 (TR) |
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High-Efficiency, Quad-Output, Main Power-
Supply Controllers for Notebook Computers
PCB Layout Guidelines
Careful PCB layout is critical to achieving low switching
losses and clean, stable operation. The switching
power stage requires particular attention (Figure 9). If
possible, mount all the power components on the top
side of the board, with their ground terminals flush
against one another. Follow these guidelines for good
PCB layout:
Keep the high-current paths short, especially at the
ground terminals. This practice is essential for stable,
jitter-free operation.
Keep the power traces and load connections short. This
practice is essential for high efficiency. Using thick cop-
per PCBs (2oz vs. 1oz) can enhance full-load efficiency
by 1% or more. Correctly routing PCB traces is a difficult
task that must be approached in terms of fractions of
centimeters, where a single milliohm of excess trace
resistance causes a measurable efficiency penalty.
Minimize current-sensing errors by connecting CSH_
and CSL_ directly across the current-sense resistor
(R SENSE_ ).
When trade-offs in trace lengths must be made, it is
preferable to allow the inductor charging path to be
made longer than the discharge path. For example, it is
better to allow some extra distance between the input
capacitors and the high-side MOSFET than to allow dis-
tance between the inductor and the low-side MOSFET
or between the inductor and the output filter capacitor.
Route high-speed switching nodes (BST_, LX_, DH_,
and DL_) away from sensitive analog areas (REF, FB_,
CSH_, CSL_).
Layout Procedure
Place the power components first, with ground termi-
nals adjacent (N L _ source, C IN , C OUT _, and D L _
anode). If possible, make all these connections on the
top layer with wide, copper-filled areas.
Mount the controller IC adjacent to the low-side MOSFET,
preferably on the back side opposite N L_ and N H_ in
order to keep LX_, GND, DH_, and the DL_ gate-drive
lines short and wide. The DL_ and DH_ gate traces must
be short and wide (50 mils to 100 mils wide if the MOSFET
is 1in from the controller IC) to keep the driver impedance
low and for proper adaptive dead-time sensing.
Group the gate-drive components (BST_ diode and
capacitor, LDO5 bypass capacitor) together near the
controller IC.
Make the DC-DC controller ground connections as
shown in Figures 1 and 9. This diagram can be viewed
as having two separate ground planes: power ground,
where all the high-power components go, and an ana-
log ground plane for sensitive analog components. The
analog ground plane and power ground plane must
meet only at a single point directly at the IC.
Connect the output power planes directly to the output
filter capacitor positive and negative terminals with mul-
tiple vias. Place the entire DC-DC converter circuit as
close to the load as is practical.
34
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