参数资料
型号: SP705EN-L
厂商: Exar Corporation
文件页数: 4/17页
文件大小: 0K
描述: IC SUPERVISOR MPU LP 8NSOIC
标准包装: 98
类型: 简单复位/加电复位
监视电压数目: 1
复位: 低有效
复位超时: 最小为 140 ms
电压 - 阀值: 4.65V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 8-SOIC(0.154",3.90mm 宽)
供应商设备封装: 8-SOIC
包装: 管件
其它名称: 1016-1226-5
S P 7 0 5 - S P 7 0 8 - S P 8 1 3 L
L o w P o w e r M i c r o p r o c e s s o r S u p e r v i s o r y C i r c u i t s
PIN ASSIGNMENT
Fig. 3: Pin Assignment
PIN DESCRIPTION
Pin Number
Name
SP705-SP706
SOIC MSOP
SP707-SP708
SOIC MSOP
SP813L
DIP
SOIC
Description
Manual Reset
MR
V CC
GND
PFI
PFO
1
2
3
4
5
3
4
5
6
-
1
2
3
4
5
3
4
5
6
7
1
2
3
4
5
This input triggers a reset pulse when pulled below 0.8V. This
active LOW input has an internal 250μA pull-up current. It
can be driven from a TTL or CMOS logic line or shorted to
ground with a switch.
+5V power supply
Ground reference for all signals
Power-Fail Input
When this voltage monitor input is less than 1.25V, PFO goes
LOW. Connect PFI to ground or V CC when not in use.
Power-Fail Output
This output is LOW until PFI is less then 1.25V
Watchdog Input
If this input remains HIGH or LOW for 1.6s, the internal
WDI
6
8
-
-
6
watchdog timer times out and WDO goes LOW. Floating WDI
or connecting WDI to a high-impedance tri-state buffer
disables the watchdog feature. The internal watchdog timer
clears whenever RESET is asserted, WDI is tri-stated, or
whenever WDI sees a rising or falling edge.
N.C.
-
-
6
8
-
No Connect
Active-LOW RESET Output
This output pulses LOW for 200ms when triggered and stays
RESET
7
1
7
1
-
LOW whenever V CC is below the reset threshold (4.65V for the
SP705/707/813L and 4.40V for the SP706/708). It remains
LOW for 200ms after V cc rises above the reset threshold or
MR goes from LOW to HIGH. A watchdog timeout will not
trigger RESET unless WDO is connected to MR .
? 2010 Exar Corporation
4/17
Rev. 2.0.0
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