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| 型号： | MAX17004ETJ+ |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 24/36页 |
| 文件大小： | 0K |
| 描述： | IC PS CTRLR FOR NOTEBOOKS 32TQFN |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 60 |
| 应用： | 控制器，笔记本电脑电源系统 |
| 输入电压： | 6 V ~ 26 V |
| 输出数： | 4 |
| 输出电压： | 3.3V，5V，2 V ~ 5.5 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-WFQFN 裸露焊盘 |
| 供应商设备封装： | 32-TQFN-EP（5x5） |
| 包装： | 管件 |
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High-Efficiency, Quad-Output, Main Power-
Supply Controllers for Notebook Computers
Table 5. Operating Modes Truth Table
MODE
Power-Up
Run
Output Overvoltage
(OVP) Protection
(MAX17003)
Output Undervoltage
Protection (UVP)
Standby
Shutdown
Thermal Shutdown
Switchover Fault
CONDITION
LDO5 < UVLO threshold
SHDN = high, ON3 or ON5 enabled
Either output > 111% of nominal level
Either output < 70% of nominal level,
UVP is enabled 6144 clock cycles
(1/f OSC ) after the output is enabled
ON5 and ON3 < startup threshold,
SHDN = high
SHDN = low
T J > +160°C
Excessive current on LDO5 switchover
transistors
COMMENT
Transitions to discharge mode after V IN POR and after REF
becomes valid. LDO5, REF remain active. DL_ is low.
Normal operation.
Exited by POR or cycling SHDN , ON3, or ON5.
Exited by POR or cycling SHDN , ON3, or ON5.
DL_ stays low. LDO5 active.
All circuitry off.
Exited by POR or cycling SHDN , ON3, or ON5.
DL3 and DL5 go low before LDO5 turns off.
Exited by POR or cycling SHDN , ON3, or ON5.
ON3 or ON5 low). Once the soft-start sequence termi-
nates, PGDALL becomes high impedance as long as
both SMPS outputs are above 90% of the nominal regu-
lation voltage set by FB. PGDALL goes low once either
SMPS output drops 10% below its nominal regulation
point, an SMPS output overvoltage fault occurs, or ON_
or SHDN is low. For a logic-level PGDALL output volt-
age, connect an external pullup resistor between
PGDALL and LDO5. A 100k Ω pullup resistor works well
in most applications.
Fault Protection
Output Overvoltage Protection (OVP)—
MAX17003 Only
If the output voltage of either SMPS rises above 111% of
its nominal regulation voltage and the OVP protection is
enabled, the controller sets the fault latch, pulls
PGDALL low, shuts down the SMPS controllers that
tripped the fault, and immediately pulls DH_ low and
forces DL_ high. This turns on the synchronous-rectifier
MOSFETs with 100% duty, rapidly discharging the out-
put capacitors and clamping both outputs to ground.
However, immediately latching DL_ high typically caus-
es slightly negative output voltages due to the energy
stored in the output LC at the instant the OVP occurs. If
the load cannot tolerate a negative voltage, place a
power Schottky diode across the output to act as a
reverse-polarity clamp. If the condition that caused the
overvoltage persists (such as a shorted high-side MOS-
FET), the battery blows. The other output is shut down
using the soft-discharge feature with DL_ forced low.
Cycle LDO5 below 1V or toggle either ON3, ON5, or
SHDN to clear the fault latch and restart the SMPS con-
trollers.
Output Undervoltage Protection (UVP)
Each SMPS controller includes an output UVP protection
circuit that begins to monitor the output 6144 clock
cycles (1/f OSC ) after that output is enabled (ON_ pulled
high). If either SMPS output voltage drops below 70% of
its nominal regulation voltage and the UVP protection is
enabled, the UVP circuit sets the fault latch, pulls
PGDALL low, and shuts down both controllers using the
soft-discharge feature with DL_ forced low. Cycle LDO5
below 1V or toggle either ON3, ON5, or SHDN to clear
the fault latch and restart the SMPS controllers.
Thermal-Fault Protection
The MAX17003/MAX17004 feature a thermal fault-pro-
tection circuit. When the junction temperature rises
above +160 ° C, a thermal sensor activates the fault
latch, pulls PGDALL low, and shuts down both SMPS
controllers using the soft-discharge feature with DL_
forced low. Toggle either ON3, ON5, or SHDN to clear
the fault latch and restart the controllers after the junc-
tion temperature cools by 15 ° C.
24
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