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参数资料
| 型号： | IDT70V657S15BF |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 13/24页 |
| 文件大小： | 0K |
| 描述： | IC SRAM 1.125MBIT 15NS 208FBGA |
| 标准包装： | 7 |
| 格式 - 存储器： | RAM |
| 存储器类型： | SRAM - 双端口，异步 |
| 存储容量： | 1.125M（32K x 36） |
| 速度： | 15ns |
| 接口： | 并联 |
| 电源电压： | 3.15 V ~ 3.45 V |
| 工作温度： | 0°C ~ 70°C |
| 封装/外壳： | 208-LFBGA |
| 供应商设备封装： | 208-CABGA（15x15） |
| 包装： | 托盘 |
| 其它名称： | 70V657S15BF |
IDT70V659/58/57S
High-Speed 3.3V 128/64/32K x 36 Asynchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Write Cycle No. 1, R/ W Controlled Timing (1,5,8)
t WC
ADDRESS
OE
t AW
t HZ
(7)
CE or SEM
(9)
BE n
(9)
t AS (6)
t WP
(2)
t WR
(3)
R/ W
t WZ (7)
t OW
DATA OUT
(4)
t DW
t DH
(4)
DATA IN
4869 drw 08
Timing Waveform of Write Cycle No. 2, CE Controlled Timing (1,5)
t WC
ADDRESS
t AW
CE or SEM
(9)
t AS
BE n
(9)
R/ W
DATA IN
(6)
t EW (2)
t DW
t WR (3)
t DH
4869 drw 09
.
NOTES:
1. R/ W or CE or BE n = V IH during all address transitions.
2. A write occurs during the overlap (t EW or t WP ) of a CE = V IL and a R/ W = V IL for memory array writing cycle.
3. t WR is measured from the earlier of CE or R/ W (or SEM or R/ W ) going HIGH to the end of write cycle.
4. During this period, the I/O pins are in the output state and input signals must not be applied.
5. If the CE or SEM = V IL transition occurs simultaneously with or after the R/ W = V IL transition, the outputs remain in the High-impedance state.
6. Timing depends on which enable signal is asserted last, CE or R/ W .
7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test Load
(Figure 2).
8. If OE = V IL during R/W controlled write cycle, the write pulse width must be the larger of t WP or (t WZ + t DW ) to allow the I/O drivers to turn off and data to be
placed on the bus for the required t DW . If OE = V IH during an R/ W controlled write cycle, this requirement does not apply and the write pulse can be as short as the
specified t WP .
9. To access RAM, CE = V IL and SEM = V IH . To access semaphore, CE = V IH and SEM = V IL . t EW must be met for either condition.
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