参数资料
型号: IDT70V657S15BF
厂商: IDT, Integrated Device Technology Inc
文件页数: 14/24页
文件大小: 0K
描述: IC SRAM 1.125MBIT 15NS 208FBGA
标准包装: 7
格式 - 存储器: RAM
存储器类型: SRAM - 双端口,异步
存储容量: 1.125M(32K x 36)
速度: 15ns
接口: 并联
电源电压: 3.15 V ~ 3.45 V
工作温度: 0°C ~ 70°C
封装/外壳: 208-LFBGA
供应商设备封装: 208-CABGA(15x15)
包装: 托盘
其它名称: 70V657S15BF
IDT70V659/58/57S
High-Speed 3.3V 128/64/32K x 36 Asynchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Semaphore Read after Write Timing, Either Side (1)
t SAA
A 0 -A 2
VALID ADDRESS
VALID ADDRESS
DATA OUT (2)
SEM / BE n (1)
I/O
t AW
t WR
t EW
t DW
DATA IN VALID
t SOP
t ACE
t OH
VALID
R/ W
t AS
t WP
t DH
OE
t SWRD
t SOP
t AOE
Write Cycle
Read Cycle
4869 drw 10
NOTES:
1. CE = V IH for the duration of the above timing (both write and read cycle) (Refer to Chip Enable Truth Table). Refer also to Truth Table II for appropriate BE controls.
2. "DATA OUT VALID" represents all I/O's (I/O 0 - I/O 35 ) equal to the semaphore value.
Timing Waveform of Semaphore Write Contention (1,3,4)
A 0"A" -A 2"A"
MATCH
SIDE
SIDE
(2)
(2)
"A"
"B"
R/ W "A"
SEM "A"
A 0"B" -A 2"B"
R/ W "B"
t SPS
MATCH
SEM "B"
4869 drw 11
.
NOTES:
1. D OR = D OL = V IL , CE L = CE R = V IH . Refer to Truth Table II for appropriate BE controls.
2. All timing is the same for left and right ports. Port "A" may be either left or right port. "B" is the opposite from port "A".
3. This parameter is measured from R/ W "A" or SEM "A" going HIGH to R/ W "B" or SEM "B" going HIGH.
4. If t SPS is not satisfied,the semaphore will fall positively to one side or the other, but there is no guarantee which side will be granted the semaphore flag.
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