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| 型号： | IDT70V657S15BF |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 19/24页 |
| 文件大小： | 0K |
| 描述： | IC SRAM 1.125MBIT 15NS 208FBGA |
| 标准包装： | 7 |
| 格式 - 存储器： | RAM |
| 存储器类型： | SRAM - 双端口，异步 |
| 存储容量： | 1.125M（32K x 36） |
| 速度： | 15ns |
| 接口： | 并联 |
| 电源电压： | 3.15 V ~ 3.45 V |
| 工作温度： | 0°C ~ 70°C |
| 封装/外壳： | 208-LFBGA |
| 供应商设备封装： | 208-CABGA（15x15） |
| 包装： | 托盘 |
| 其它名称： | 70V657S15BF |
IDT70V659/58/57S
High-Speed 3.3V 128/64/32K x 36 Asynchronous Dual-Port Static RAM
Truth Table IV —
Address BUSY Arbitration
Industrial and Commercial Temperature Ranges
Inputs
Outputs
CE L
X
H
X
L
CE R
X
X
H
L
A OL -A 16L (4)
A OR -A 16R
NO MATCH
MATCH
MATCH
MATCH
BUSY L (1)
H
H
H
(2)
BUSY R (1)
H
H
H
(2)
Function
Normal
Normal
Normal
Write Inhibit (3)
4869 tbl 17
NOTES:
1. Pins BUSY L and BUSY R are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BUSY outputs on the
IDT70V659/58/57 are push-pull, not open drain outputs. On slaves the BUSY input internally inhibits writes.
2. "L" if the inputs to the opposite port were stable prior to the address and enable inputs of this port. "H" if the inputs to the opposite port became stable after the address
and enable inputs of this port. If t APS is not met, either BUSY L or BUSY R = LOW will result. BUSY L and BUSY R outputs can not be LOW simultaneously.
3. Writes to the left port are internally ignored when BUSY L outputs are driving LOW regardless of actual logic level on the pin. Writes to the right port are internally ignored
when BUSY R outputs are driving LOW regardless of actual logic level on the pin.
4. A 16X is a NC for IDT70V658, therefore Address comparison will be for A 0 - A 15 . Also, A 16X and A 15X are NC's for IDT70V657, therefore Address comparison will
be for A 0 - A 14 .
Truth Table V — Example of Semaphore Procurement Sequence (1,2,3)
Functions
No Action
Left Port Writes "0" to Semaphore
Right Port Writes "0" to Semaphore
Left Port Writes "1" to Semaphore
Left Port Writes "0" to Semaphore
Right Port Writes "1" to Semaphore
Left Port Writes "1" to Semaphore
Right Port Writes "0" to Semaphore
Right Port Writes "1" to Semaphore
Left Port Writes "0" to Semaphore
Left Port Writes "1" to Semaphore
NOTES:
D 0 - D 35 Left
1
0
0
1
1
0
1
1
1
0
1
D 0 - D 35 Right
1
1
1
0
0
1
1
0
1
1
1
Status
Semaphore free
Left port has semaphore token
No change. Right side has no write access to semaphore
Right port obtains semaphore token
No change. Left port has no write access to semaphore
Left port obtains semaphore token
Semaphore free
Right port has semaphore token
Semaphore free
Left port has semaphore token
Semaphore free
4869 tbl 18
1. This table denotes a sequence of events for only one of the eight semaphores on the IDT70V659/58/57.
2. There are eight semaphore flags written to via I/O 0 and read from all I/O's (I/O 0 -I/O 35 ). These eight semaphores are addressed by A 0 - A 2 .
3. CE = V IH , SEM = V IL to access the semaphores. Refer to the Semaphore Read/Write Control Truth Table.
Functional Description
The IDT70V659/58/57 provides two ports with separate control,
address and I/O pins that permit independent access for reads or writes
to any location in memory. The IDT70V659/58/57 has an automatic power
down feature controlled by CE . The CE 0 and CE 1 control the on-chip
power down circuitry that permits the respective port to go into a standby
mode when not selected ( CE = HIGH). When a port is enabled, access
to the entire memory array is permitted.
19
Interrupts
If the user chooses the interrupt function, a memory location (mail box
or message center) is assigned to each port. The left port interrupt flag
( INT L ) is asserted when the right port writes to memory location 1FFFE
(HEX) (FFFE for IDT70V658 and 7FFE for IDT70V657), where a write
is defined as CE R = R/ W R = V IL per the Truth Table III. The left port clears
the interrupt through access of address location 1FFFE (FFFE for
IDT70V658 and 7FFE for IDT70V657) when CE L = OE L = V IL , R/ W is
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