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参数资料
| 型号： | MPC740PRX400RE |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 400 MHz, RISC PROCESSOR, CBGA255 |
| 封装： | 21 X 21 MM, 3 MM HEIGHT, 1.27 MM PITCH, CERAMIC, BGA-255 |
| 文件页数： | 5/24页 |
| 文件大小： | 543K |
| 代理商： | MPC740PRX400RE |
XPC750P RISC Microprocessor Hardware Specications
13
PRELIMINARYSUBJECT TO CHANGE WITHOUT NOTICE
Electrical and Thermal Characteristics
multiplied up to the core frequency and divided down to the L2CLK frequency). In other words, the AC
timings of Table 12. and Table 13. are entirely independent of L2SYNC_IN. In a closed loop system, where
L2SYNC_IN is driven through the board trace by L2SYNC_OUT, L2SYNC_IN only controls the output
phase of L2CLKOUTA and L2CLKOUTB which are used to latch or enable data at the SRAMs. However,
since in a closed loop system L2SYNC_IN is held in phase alignment with the internal L2CLK, the signals
of Table 12. and Table 13. are referenced to this signal rather than the not-externally-visible internal
L2CLK. During manufacturing test, these times are actually measured relative to SYSCLK.
Table 11. L2CLK Output AC Timing Specifications
At recommended operating conditions (See Table 3.)
Num
Characteristic
300 MHz
333 MHz
366 MHz
400 MHz
Unit
Notes
Min
Max
Min
Max
Min
Max
Min
Max
L2CLK frequency
80
300
80
333
80
366
80
400
MHz
1,4
22
L2CLK cycle time
3.3
12.5
3
12.5
2.7
12.5
2.5
12.5
ns
23
L2CLK duty cycle
50
%
2
Internal DLL-relock
time
640
640
640
640
L2CLK
3
DLL capture window
0.5
12.5
0.5
12.5
0.5
12.5
0.5
12.5
ns
5
L2CLKOUT output-to-
output skew
50
ps
6
L2CLKOUT output jitter
±150
ps
6
Notes:
1. L2CLK outputs are L2CLK_OUTA, L2CLK_OUTB, L2CLK_OUTC, L2CLK_OUTD, and L2SYNC_OUT pins.
The L2CLK frequency to core frequency settings must be chosen such that the resulting L2CLK frequency
and core frequency do not exceed their respective maximum or minimum operating frequencies. The
maximum L2LCK frequency will be system dependent. L2CLK_OUTA and L2CLK_OUTB must have equal
loading.
2. The nominal duty cycle of the L2CLK is 50% measured at midpoint voltage.
3. The DLL re-lock time is specied in terms of L2CLKs. The number in the table must be multiplied by the
period of L2CLK to compute the actual time duration in nanoseconds. Re-lock timing is guaranteed by
design and characterization.
4. The L2CR[L2SL] bit should be set for L2CLK frequencies less than 110 MHz. This adds more delay to each
tap of the DLL.
5. Allowable skew between L2SYNC_OUT and L2SYNC_IN. The minimum skew value allows several taps of
negative adjustment without rolling over to the maximum tap. Exceptionally short paths from L2SYNC_OUT
to L2SYNC_IN on the XPC750P has been observed to result in missing L2CLKOUT pulses or L2CLKOUT
pulses of incorrect duty cycle.
6. Guaranteed by design and not tested. This output jitter number represents the maximum delay of one tap
forward or one tap back from the current DLL tap as the phase comparator seeks to minimize the phase
difference between L2SYNC_IN and the internal L2CLK. This number must be comprehended in the L2
timing analysis. The input jitter on SYSCLK affects L2CLKOUT and the L2 address/data/control signals
equally and therefore is already comprehended in the AC timing and does not have to be considered in the
L2 timing analysis.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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