参数资料
型号: MPC8245TVV266D
厂商: MOTOROLA INC
元件分类: 微控制器/微处理器
英文描述: 32-BIT, 266 MHz, RISC PROCESSOR, PBGA352
封装: 35 X 35 MM, 1.70 MM HEIGHT, 1.27 MM PITCH, CAVITY-UP, TBGA-352
文件页数: 15/60页
文件大小: 674K
代理商: MPC8245TVV266D
22
MPC8245 Integrated Processor Hardware Specications
MOTOROLA
Electrical and Thermal Characteristics
Figure 12. AC Test Load for the MPC8245
14b
SDRAM_SYNC_IN to output high impedance (for all others)
4.0
ns
2
Notes:
1. All PCI signals are measured from GVDD/2 of the rising edge of PCI_SYNC_IN to 0.285 × OVDD or 0.615 × OVDD
of the signal in question for 3.3 V PCI signaling levels. See Figure 10.
2. All memory and related interface output signal specications are specied from the VM = 1.4 V of the rising edge
of the memory bus clock, SDRAM_SYNC_IN to the TTL level (0.8 or 2.0 V) of the signal in question.
SDRAM_SYNC_IN is the same as PCI_SYNC_IN in 1:1 mode, but is twice the frequency in 2:1 mode
(processor/memory bus clock rising edges occur on every rising and falling edge of PCI_SYNC_IN). See Figure 9.
3. PCI bused signals are composed of the following signals: LOCK, IRDY, C/BE[3:0], PAR, TRDY, FRAME, STOP,
DEVSEL, PERR, SERR, AD[31:0], REQ[4:0], GNT[4:0], IDSEL, INTA.
4. In order to meet minimum output hold specications relative to PCI_SYNC_IN for both 33- and 66-MHz PCI
systems, the MPC8245 has a programmable output hold delay for PCI signals (the PCI_SYNC_IN to output valid
timing is also affected). The initial value of the output hold delay is determined by the values on the MCP and CKE
reset conguration signals; the values on these two signals are inverted then stored as the initial settings of
PCI_HOLD_DEL = PMCR2[5:4] (power management conguration register 2 <0x72>), respectively. Since MCP
and CKE have internal pull-up resistors, the default value of PCI_HOLD_DEL after reset is 0b00. Further output
hold delay values are available by programming the PCI_HOLD_DEL value of the PMCR2 conguration register.
Table 11. Output AC Timing Specications (continued)
Num
Characteristic
Min
Max
Unit
Notes
Output
Z0 = 50
OVDD/2 for PCI
RL = 50
Output Measurements are Made at the Device Pin
GVDD/2 for Memory
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