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参数资料
| 型号： | LC4384C-75T176I |
| 厂商： | Lattice Semiconductor Corporation |
| 文件页数： | 2/99页 |
| 文件大小： | 0K |
| 描述： | IC PLD 384MC 128IO 7.5NS 176TQFP |
| 标准包装： | 40 |
| 系列： | ispMACH® 4000C |
| 可编程类型： | 系统内可编程 |
| 最大延迟时间 tpd(1)： | 7.5ns |
| 电压电源 - 内部： | 1.65 V ~ 1.95 V |
| 逻辑元件/逻辑块数目： | 24 |
| 宏单元数： | 384 |
| 输入/输出数： | 128 |
| 工作温度： | -40°C ~ 105°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 176-LQFP |
| 供应商设备封装： | 176-TQFP（24x24） |
| 包装： | 托盘 |
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Lattice Semiconductor
Table 2. ispMACH 4000Z Family Selection Guide
ispMACH 4000V/B/C/Z Family Data Sheet
ispMACH 4032ZC
ispMACH 4064ZC
ispMACH 4128ZC
ispMACH 4256ZC
Macrocells
I/O + Dedicated Inputs
32
32+4/32+4
64
32+4/32+12/
128
64+10/96+4
256
64+10/96+6/
64+10/64+10
128+4
t PD (ns)
t S (ns)
t CO (ns)
f MAX (MHz)
Supply Voltage (V)
Max. Standby Icc (μA)
Pins/Package
3.5
2.2
3.0
267
1.8
20
48 TQFP
3.7
2.5
3.2
250
1.8
25
48 TQFP
4.2
2.7
3.5
220
1.8
35
4.5
2.9
3.8
200
1.8
55
56 csBGA
56 csBGA
100 TQFP
132 csBGA
100 TQFP
132csBGA
100 TQFP
132 csBGA
176 TQFP
ispMACH 4000 Introduction
The high performance ispMACH 4000 family from Lattice offers a SuperFAST CPLD solution. The family is a blend
of Lattice’s two most popular architectures: the ispLSI ? 2000 and ispMACH 4A. Retaining the best of both families,
the ispMACH 4000 architecture focuses on significant innovations to combine the highest performance with low
power in a flexible CPLD family.
The ispMACH 4000 combines high speed and low power with the flexibility needed for ease of design. With its
robust Global Routing Pool and Output Routing Pool, this family delivers excellent First-Time-Fit, timing predictabil-
ity, routing, pin-out retention and density migration.
The ispMACH 4000 family offers densities ranging from 32 to 512 macrocells. There are multiple density-I/O com-
binations in Thin Quad Flat Pack (TQFP), Chip Scale BGA (csBGA) and Fine Pitch Thin BGA (ftBGA) packages
ranging from 44 to 256 pins/balls. Table 1 shows the macrocell, package and I/O options, along with other key
parameters.
The ispMACH 4000 family has enhanced system integration capabilities. It supports 3.3V (4000V), 2.5V (4000B)
and 1.8V (4000C/Z) supply voltages and 3.3V, 2.5V and 1.8V interface voltages. Additionally, inputs can be safely
driven up to 5.5V when an I/O bank is configured for 3.3V operation, making this family 5V tolerant. The ispMACH
4000 also offers enhanced I/O features such as slew rate control, PCI compatibility, bus-keeper latches, pull-up
resistors, pull-down resistors, open drain outputs and hot socketing. The ispMACH 4000 family members are 3.3V/
2.5V/1.8V in-system programmable through the IEEE Standard 1532 interface. IEEE Standard 1149.1 boundary
scan testing capability also allows product testing on automated test equipment. The 1532 interface signals TCK,
TMS, TDI and TDO are referenced to V CC (logic core).
Overview
The ispMACH 4000 devices consist of multiple 36-input, 16-macrocell Generic Logic Blocks (GLBs) interconnected
by a Global Routing Pool (GRP). Output Routing Pools (ORPs) connect the GLBs to the I/O Blocks (IOBs), which
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