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| 型号： | ICL7650CSD |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 11/12页 |
| 文件大小： | 0K |
| 描述： | IC OPAMP CHOPPER/STABLE 14-SOIC |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 50 |
| 放大器类型： | 断路器（零漂移） |
| 电路数： | 1 |
| 转换速率： | 2.5 V/µs |
| 增益带宽积： | 2MHz |
| 电流 - 输入偏压： | 1.5pA |
| 电压 - 输入偏移： | 700µV |
| 电流 - 电源： | 1.2mA |
| 电压 - 电源，单路/双路(±)： | 4.5 V ~ 16 V，±2.25 V ~ 8 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 14-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 14-SOIC |
| 包装： | 管件 |
ICL7650/ICL7650B/ICL7653/ICL7653B
Chopper-Stabilized Op Amps
8
_______________________________________________________________________________________
Input Guarding
Low-leakage, high-impedance CMOS inputs allow the
ICL7650/ICL7653 to measure high-impedance sources.
Stray leakage paths can decrease input resistance and
increase input currents unless inputs are guarded.
Boards must be thoroughly cleaned with TCE or alcohol
and blown dry with compressed air. The board should
be coated with epoxy or silicone after cleaning to pre-
vent contamination.
Leakage currents may cause trouble even with properly
cleaned and coated boards, particularly since the input
pins are adjacent to pins that are at supply potentials.
Leakage can be significantly reduced by using guard-
ing to decrease the voltage difference between inputs
and adjacent metal runs. Use a 10-lead pin circle, with
the leads of the device formed so that the holes adja-
cent to the inputs are empty when it is inserted in the
board to accomplish input guarding of the 8-pin TO-99
package. A conductive ring surrounding the inputs, the
“guard,” is connected to a low-impedance point that is
approximately the same voltage as the inputs. The
guard then absorbs the leakage current from the high-
voltage pins. Typical guard connections are shown in
Figure 3.
OUTPUT
INVERTING AMPLIFIER
FOLLOWER
INPUT
R2
R1
R3*
OUTPUT
INPUT
USE R3 TO COMPENSATE FOR LARGE
SOURCE RESISTANCES, OR FOR CLAMP
OPERATION (FIGURE 5).
*
NONINVERTING AMPLIFIER
R3*
OUTPUT
INPUT
R2
R1
NOTE:
SHOULD BE LOW IMPEDANCE FOR
OPTIMUM GUARDING.
R1 R2
R1 + R2
BOTTOM VIEW
BOARD LAYOUT FOR INPUT GUARDING
WITH TO-99 PACKAGE.
1
V+
V-
GUARD
INPUTS
OUTPUT
EXTERNAL
CAPACITORS
EXTERNAL
CAPACITORS
8
7
6
5
4 3
2
Figure 3. Input Guard Connection
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