参数资料
型号: NHI-1598ET/883
厂商: NATIONAL HYBRID INC
元件分类: 微控制器/微处理器
英文描述: 2 CHANNEL(S), MIL-STD-1553 CONTROLLER, CPGA69
封装: 1.100 X 1.100 INCH, CERAMIC, PLUG IN, PGA-69
文件页数: 6/89页
文件大小: 569K
代理商: NHI-1598ET/883
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13
The MPU performs the following functions:
Recognizes the various message types (for BC, MT, and RT) and responds with the
appropriate sequence of control signals.
Validates format and timing of received data words.
Checks command legality.
Responds with status/ data.
Calculates all addresses for accessing the RAM and discrete I/ O.
Updates RAM data table contents, including tag words.
Optionally time tags data tables.
Issues interrupt requests to the ICU.
The maximum response time of the NHi- ET in the RT mode is less than 6.0
microseconds (measured from zero- cross to zero- cross).
3.4.0
RT HARDWIRE TERMINAL ADDRESS
The terminal address of the NHi- ET can be hardwired using I/ O DAT( 5: 0). I/ O DAT( 4: 0) are
used for the terminal address, I/ O DAT0 being the LSB, and I/ O DAT5 is used to set odd parity
in the address. These pins CANNOT be directly connected to +5 or ground since the I/ O data
bus drives the NHi- ET's internal RAM.
The address must be wired using pull- up and pull- down resistors. There are 64K internal pull- up
resistors in the protocol chip, so only external pull- down resistors of 4.7K are required. The
Hardwire Address is read and loaded into the terminal at Power- On Reset, Hardware Reset, and
Software Reset.
The terminal address can be changed at any time through software by writing a new address to
the Basic Status Register, however, if any of the above resets occur, the Hardwire Address will
be re- loaded into the terminal. The software address can be locked out by setting Bit2 in
Configuration Register 1.
4.0.0
DATA STRUCTURE
4.1.0
ADDRESS MAP
The NHi- ET appears to the host as 16K or 64K words of memory divided into the following
blocks:
ADDRESS RANGE
DESCRIPTION
0 -- 30
INTERNAL REGISTERS
31
I/O TAG WORD
32 -- 35
I/O SPACE
64 -- 16383/65535
SHARED RAM
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