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参数资料
型号： PIC16C73A-20/SO
厂商： Microchip Technology
文件页数： 16/114页
文件大小： 0K
描述： IC MCU OTP 4KX14 A/D PWM 28SOIC
产品培训模块： Asynchronous Stimulus
8-bit PIC® Microcontroller Portfolio
标准包装： 27
系列： PIC® 16C
核心处理器： PIC
芯体尺寸： 8-位
速度： 20MHz
连通性： I²C，SPI，UART/USART
外围设备： 欠压检测/复位，POR，PWM，WDT
输入/输出数： 22
程序存储器容量： 7KB（4K x 14）
程序存储器类型： OTP
RAM 容量： 192 x 8
电压 - 电源 (Vcc/Vdd)： 4 V ~ 6 V
数据转换器： A/D 5x8b
振荡器型： 外部
工作温度： 0°C ~ 70°C
封装/外壳： 28-SOIC（0.295"，7.50mm 宽）
包装： 管件
配用： XLT28SO-1-ND - SOCKET TRANSITION 28SOIC 300MIL
309-1073-ND - ADAPTER 28-SOIC TO 28-SOIC
309-1024-ND - ADAPTER 28-SOIC TO 28-DIP
309-1023-ND - ADAPTER 28-SOIC TO 28-DIP
PIC16C7X
DS30390E-page 112
1997 Microchip Technology Inc.
12.3.2
USART SYNCHRONOUS MASTER
RECEPTION
Once Synchronous mode is selected, reception is
enabled
by
setting
either
enable
bit
SREN
(RCSTA<5>) or enable bit CREN (RCSTA<4>). Data is
sampled on the RC7/RX/DT pin on the falling edge of
the clock. If enable bit SREN is set, then only a single
word is received. If enable bit CREN is set, the recep-
tion is continuous until CREN is cleared. If both bits are
set then CREN takes precedence. After clocking the
last bit, the received data in the Receive Shift Register
(RSR) is transferred to the RCREG register (if it is
empty). When the transfer is complete, interrupt ag bit
RCIF (PIR1<5>) is set. The actual interrupt can be
enabled/disabled by setting/clearing enable bit RCIE
(PIE1<5>). Flag bit RCIF is a read only bit which is
reset by the hardware. In this case it is reset when the
RCREG register has been read and is empty. The
RCREG is a double buffered register, i.e. it is a two
deep FIFO. It is possible for two bytes of data to be
received and transferred to the RCREG FIFO and a
third byte to begin shifting into the RSR register. On the
clocking of the last bit of the third byte, if the RCREG
register is still full then overrun error bit OERR
(RCSTA<1>) is set. The word in the RSR will be lost.
The RCREG register can be read twice to retrieve the
two bytes in the FIFO. Bit OERR has to be cleared in
software (by clearing bit CREN). If bit OERR is set,
transfers from the RSR to the RCREG are inhibited, so
it is essential to clear bit OERR if it is set. The 9th
receive bit is buffered the same way as the receive
data. Reading the RCREG register, will load bit RX9D
with a new value, therefore it is essential for the user to
read the RCSTA register before reading RCREG in
order not to lose the old RX9D information.
Steps to follow when setting up a Synchronous Master
Reception:
1.
Initialize the SPBRG register for the appropriate
baud rate. (Section 12.1)
2.
Enable the synchronous master serial port by
setting bits SYNC, SPEN, and CSRC.
3.
Ensure bits CREN and SREN are clear.
4.
If interrupts are desired, then set enable bit
RCIE.
5.
If 9-bit reception is desired, then set bit RX9.
6.
If a single reception is required, set bit SREN.
For continuous reception set bit CREN.
7.
Interrupt ag bit RCIF will be set when reception
is complete and an interrupt will be generated if
enable bit RCIE was set.
8.
Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
9.
Read the 8-bit received data by reading the
RCREG register.
10. If any error occurred, clear the error by clearing
bit CREN.
TABLE 12-9:
REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR,
BOR
Value on all
other Resets
0Ch
PIR1
PSPIF(1)
ADIF
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
0000 0000
18h
RCSTA
SPEN
RX9
SREN
CREN
—
FERR
OERR
RX9D
0000 -00x
1Ah
RCREG
USART Receive Register
0000 0000
8Ch
PIE1
PSPIE(1)
ADIE
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
0000 0000
98h
TXSTA
CSRC
TX9
TXEN
SYNC
—
BRGH
TRMT
TX9D
0000 -010
99h
SPBRG
Baud Rate Generator Register
0000 0000
Legend: x = unknown, - = unimplemented read as '0'. Shaded cells are not used for Synchronous Master Reception.
Note 1:
Bits PSPIE and PSPIF are reserved on the PIC16C73/73A/76, always maintain these bits clear.
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