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| 型号： | PC28F256J3C-115 |
| 厂商： | Intel Corp. |
| 英文描述： | Intel StrataFlash Memory (J3) |
| 中文描述： | 英特尔StrataFlash存储器（J3） |
| 文件页数： | 26/72页 |
| 文件大小： | 905K |
| 代理商： | PC28F256J3C-115 |
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256-Mbit J3 (x8/x16)
26
Datasheet
7.2
Write Operations
Table 9. Write Operations
Versions
Valid for All
Speeds
Unit
Notes
#
Symbol
Parameter
Min
Max
W1
t
PHWL
(t
PHEL
)
RP# High Recovery to WE# (CE
X
) Going Low
1
μs
1,2,3
W2
t
ELWL
(t
WLEL
)
t
WP
CE
X
(WE#) Low to WE# (CE
X
) Going Low
Write Pulse Width
0
ns
1,2,4
W3
70
ns
1,2,4
W4
t
DVWH
(t
DVEH
)
Data Setup to WE# (CE
X
) Going High
50
ns
1,2,5
W5
t
AVWH
(t
AVEH
)
t
WHEH
(t
EHWH
)
Address Setup to WE# (CE
X
) Going High
CE
X
(WE#) Hold from WE# (CE
X
) High
55
ns
1,2,5
W6
0
ns
1,2,
W7
t
WHDX
(t
EHDX
)
Data Hold from WE# (CE
X
) High
0
ns
1,2,
W8
t
WHAX
(t
EHAX
)
t
WPH
Address Hold from WE# (CE
X
) High
Write Pulse Width High
0
ns
1,2,
W9
30
ns
1,2,6
W11
t
VPWH
(t
VPEH
)
V
PEN
Setup to WE# (CE
X
) Going High
0
ns
1,2,3
W12
t
WHGL
(t
EHGL
)
t
WHRL
(t
EHRL
)
Write Recovery before Read
35
ns
1,2,7
W13
WE# (CE
X
) High to STS Going Low
500
ns
1,2,8
W15
t
QVVL
V
PEN
Hold from Valid SRD, STS Going High
0
ns
1,2,3,8,9
NOTES:
CE
X
low is defined as the first edge of CE0, CE1, or CE2 that enables the device. CE
X
high is defined at the first edge of CE0, CE1,
or CE2 that disables the device (see
Table 13
).
1. Read timing characteristics during block erase, program, and lock-bit configuration operations are the same as
during read-only operations. Refer to
AC Characteristics–Read-Only Operations
.
2. A write operation can be initiated and terminated with either CE
X
or WE#.
3. Sampled, not 100% tested.
4. Write pulse width (t
WP
) is defined from CE
X
or WE# going low (whichever goes low last) to CE
X
or WE# going
high (whichever goes high first). Hence, t
WP
= t
WLWH
= t
ELEH
= t
WLEH
= t
ELWH
.
5. Refer to
Table 14
for valid A
IN
and D
IN
for block erase, program, or lock-bit configuration.
6. Write pulse width high (t
WPH
) is defined from CE
X
or WE# going high (whichever goes high first) to CE
X
or WE#
going low (whichever goes low first). Hence, t
WPH
= t
WHWL
= t
EHEL
= t
WHEL
= t
EHWL
.
7. For array access, t
AVQV
is required in addition to t
WHGL
for any accesses after a write.
8. STS timings are based on STS configured in its RY/BY# default mode.
9. V
should be held at V
PENH
until determination of block erase, program, or lock-bit configuration success
(SR[1,3,4:5] = 0).
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