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| 型号： | PC28F256J3C-115 |
| 厂商： | Intel Corp. |
| 英文描述： | Intel StrataFlash Memory (J3) |
| 中文描述： | 英特尔StrataFlash存储器（J3） |
| 文件页数： | 31/72页 |
| 文件大小： | 905K |
| 代理商： | PC28F256J3C-115 |
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256-Mbit J3 (x8/x16)
Datasheet
31
8.0
Power and Reset Specifications
This section provides an overview of system level considerations for the Intel StrataFlash
memory family device. This section provides a brief description of power-up, power-down,
decoupling and reset design considerations.
8.1
Power-Up/Down Characteristics
In order to prevent any condition that may result in a spurious write or erase operation, it is
recommended to power-up and power-down VCC and VCCQ together. It is also recommended to
power-up VPEN with or slightly after VCC. Conversely, VPEN must power down with or slightly
before VCC.
8.2
Power Supply Decoupling
When the device is enabled, many internal conditions change. Circuits are energized, charge pumps
are switched on, and internal voltage nodes are ramped. All of this internal activities produce
transient signals. The magnitude of the transient signals depends on the device and system loading.
To minimize the effect of these transient signals, a 0.1 μF ceramic capacitor is required across each
VCC/VSS and VCCQ
signal
. Capacitors should be placed as close as possible to device
connections.
Additionally, for every eight flash devices, a 4.7 μF electrolytic capacitor should be placed between
VCC and VSS at the power supply connection. This 4.7 μF capacitor should help overcome
voltage slumps caused by PCB (printed circuit board) trace inductance.
8.3
Reset Characteristics
By holding the flash device in reset during power-up and power-down transitions, invalid bus
conditions may be masked. The flash device enters reset mode when RP# is driven low. In reset,
internal flash circuitry is disabled and outputs are placed in a high-impedance state. After return
from reset, a certain amount of time is required before the flash device is able to perform normal
operations. After return from reset, the flash device defaults to asynchronous page mode. If RP# is
driven low during a program or erase operation, the program or erase operation will be aborted and
the memory contents at the aborted block or address are no longer valid. See
Figure 14, “AC
Waveform for Reset Operation” on page 29
for detailed information regarding reset timings.
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相关代理商/技术参数 |
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| PC28F256J3C-120 | 制造商:INTEL 制造商全称:Intel Corporation 功能描述:Intel StrataFlash Memory (J3) |
| PC28F256J3C125 | 制造商:INTEL 制造商全称:Intel Corporation 功能描述:Intel StrataFlash?? Memory |
| PC28F256J3C-125 | 制造商:INTEL 制造商全称:Intel Corporation 功能描述:Intel StrataFlash Memory (J3) |
| PC28F256J3C125 S B93 | 制造商:Intel 功能描述: |
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