- 您现在的位置：买卖IC网 > PDF目录369948 > PC28F256J3C-115 (Intel Corp.) Intel StrataFlash Memory (J3) PDF资料下载
参数资料
| 型号： | PC28F256J3C-115 |
| 厂商： | Intel Corp. |
| 英文描述： | Intel StrataFlash Memory (J3) |
| 中文描述： | 英特尔StrataFlash存储器（J3） |
| 文件页数： | 34/72页 |
| 文件大小： | 905K |
| 代理商： | PC28F256J3C-115 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页当前第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页
256-Mbit J3 (x8/x16)
34
Datasheet
9.1.4
Standby
CE0, CE1, and CE2 can disable the device (see
Table 13 on page 33
) and place it in standby mode.
This manipulation of CEx substantially reduces device power consumption. D[15:0] outputs are
placed in a high-impedance state independent of OE#. If deselected during block erase, program, or
lock-bit configuration, the WSM continues functioning, and consuming active power until the
operation completes.
9.1.5
Reset/Power-Down
RP# at V
IL
initiates the reset/power-down mode.
In read modes, RP#-low deselects the memory, places output drivers in a high-impedance state, and
turns off numerous internal circuits. RP# must be held low for a minimum of t
PLPH
. Time t
PHQV
is
required after return from reset mode until initial memory access outputs are valid. After this wake-
up interval, normal operation is restored. The CUI is reset to read array mode and Status Register is
set to 0x80.
During block erase, program, or lock-bit configuration modes, RP#-low will abort the operation. In
default mode, STS transitions low and remains low for a maximum time of t
PLPH
+ t
PHRH
until the
reset operation is complete. Memory contents being altered are no longer valid; the data may be
partially corrupted after a program or partially altered after an erase or lock-bit configuration. Time
t
PHWL
is required after RP# goes to logic-high (V
IH
) before another command can be written.
As with any automated device, it is important to assert RP# during system reset. When the system
comes out of reset, it expects to read from the flash memory. Automated flash memories provide
status information when accessed during block erase, program, or lock-bit configuration modes. If
a CPU reset occurs with no flash memory reset, proper initialization may not occur because the
flash memory may be providing status information instead of array data. Intel StrataFlash
memory family devices allow proper initialization following a system reset through the use of the
RP# input. In this application, RP# is controlled by the same RESET# signal that resets the system
CPU.
相关PDF资料 |
PDF描述 |
|---|---|
| PC28F128J3C-115 | Intel StrataFlash Memory (J3) |
| PC28F640J3C-115 | Intel StrataFlash Memory (J3) |
| PC28F320J3C-115 | Intel StrataFlash Memory (J3) |
| PC28F128J3C-120 | Intel StrataFlash Memory (J3) |
| PC28F128J3C-125 | Intel StrataFlash Memory (J3) |
相关代理商/技术参数 |
参数描述 |
|---|---|
| PC28F256J3C-120 | 制造商:INTEL 制造商全称:Intel Corporation 功能描述:Intel StrataFlash Memory (J3) |
| PC28F256J3C125 | 制造商:INTEL 制造商全称:Intel Corporation 功能描述:Intel StrataFlash?? Memory |
| PC28F256J3C-125 | 制造商:INTEL 制造商全称:Intel Corporation 功能描述:Intel StrataFlash Memory (J3) |
| PC28F256J3C125 S B93 | 制造商:Intel 功能描述: |
| PC28F256J3C-150 | 制造商:INTEL 制造商全称:Intel Corporation 功能描述:Intel StrataFlash Memory (J3) |
发布紧急采购，3分钟左右您将得到回复。