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| 型号： | PC28F256J3C-115 |
| 厂商： | Intel Corp. |
| 英文描述： | Intel StrataFlash Memory (J3) |
| 中文描述： | 英特尔StrataFlash存储器（J3） |
| 文件页数： | 50/72页 |
| 文件大小： | 905K |
| 代理商： | PC28F256J3C-115 |
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256-Mbit J3 (x8/x16)
50
Datasheet
14.0
Special Modes
This section describes how to read the status, ID, and CFI registers. This section also details how to
configure the STS signal.
14.1
Set Read Configuration Register Command
This command is no longer supported on J3A or J3C. The J3A device will ignore this command,
while the J3C device will
result in an invalid command sequence (SR.4 and SR.5 =1).
14.2
Status (STS)
The Status (STS) signal can be configured to different states using the Configuration command.
Once the STS signal has been configured, it remains in that configuration until another
configuration command is issued or RP# is asserted low. Initially, the STS signal defaults to RY/
BY# operation where RY/BY# low indicates that the WSM is busy. RY/BY# high indicates that the
state machine is ready for a new operation or suspended.
Table 22, “STS Configuration Coding
Definitions” on page 50
displays the possible STS configurations.
To reconfigure the Status (STS) signal to other modes, the Configuration command is given
followed by the desired configuration code. The three alternate configurations are all pulse mode
for use as a system interrupt as described below. For these configurations, bit 0 controls Erase
Complete interrupt pulse, and bit 1 controls Program Complete interrupt pulse. Supplying the 0x00
configuration code with the Configuration command resets the STS signal to the default RY/BY#
level mode. The possible configurations and their usage are described in
Table 22, “STS
Configuration Coding Definitions” on page 50
. The Configuration command may only be given
when the device is not busy or suspended. Check SR.7 for device status. An invalid configuration
code will result in both SR.4 and SR.5 being set. When configured in one of the pulse modes, the
STS signal pulses low with a typical pulse width of 250 ns.
Table 22. STS Configuration Coding Definitions
D7
D6
D5
D4
D3
D2
D1
D0
Reserved
Pulse on
Program
Complete
(1)
Pulse on
Erase
Complete
(1)
D[1:0]
= STS Configuration Codes
Notes
00 = default, level mode;
device ready indication
Used to control HOLD to a memory controller to prevent accessing a
flash memory subsystem while any flash device's WSM is busy.
01 = pulse on Erase Complete
Used to generate a system interrupt pulse when any flash device in
an array has completed a block erase. Helpful for reformatting blocks
after file system free space reclamation or “cleanup.”
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