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| 型号： | PC28F256J3C-115 |
| 厂商： | Intel Corp. |
| 英文描述： | Intel StrataFlash Memory (J3) |
| 中文描述： | 英特尔StrataFlash存储器（J3） |
| 文件页数： | 61/72页 |
| 文件大小： | 905K |
| 代理商： | PC28F256J3C-115 |
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256-Mbit J3 (x8/x16)
Datasheet
61
Figure 20. Byte/Word Program Flowchart
Start
Write 40H,
Address
Write Data and
Address
Read Status
Register
SR.7 =
Full Status
Check if Desired
Byte/Word
Program Complete
Read Status
Register Data
(See Above)
Voltage Range Error
Device Protect Error
Programming Error
Byte/Word
Program
Successful
SR.3 =
SR.1 =
SR.4 =
FULL STATUS CHECK PROCEDURE
Bus
Operation
Write
Write
Standby
1. Toggling OE# (low to high to low) updates the status register. This
can be done in place of issuing the Read Status Register command.
Repeat for subsequent programming operations.
SR full status check can be done after each program operation, or
after a sequence of programming operations.
Write FFH after the last program operation to place device in read
array mode.
Bus
Operation
Standby
Standby
Toggling OE# (low to high to low) updates the status register. This can
be done in place of issuing the Read Status Register command.
Repeat for subsequent programming operations.
SR.4, SR.3 and SR.1 are only cleared by the Clear Status Register
command in cases where multiple locations are programmed before
full status is checked.
If an error is detected, clear the status register before attempting retry
or other error recovery.
0
1
1
0
1
0
1
0
Command
Setup Byte/
Word Program
Byte/Word
Program
Comments
Data = 40H
Addr = Location to Be Programmed
Data = Data to Be Programmed
Addr = Location to Be Programmed
Check SR.7
1 = WSM Ready
0 = WSM Busy
Command
Comments
Check SR.3
1 = Programming to Voltage Error
Detect
Check SR.4
1 = Programming Error
Read
(Note 1)
Status Register Data
Standby
Check SR.1
1 = Device Protect Detect
RP# = V
, Block Lock-Bit Is Set
Only required for systems
implemeting lock-bit configuration.
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