参数资料
型号: PCM1792DBR
厂商: Texas Instruments
文件页数: 16/61页
文件大小: 0K
描述: IC DAC 24BIT STER 192KHZ 28-SSOP
产品培训模块: Data Converter Basics
标准包装: 2,000
位数: 24
数据接口: I²C,串行,SPI?
转换器数目: 2
电压电源: 模拟和数字
工作温度: -25°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 28-SSOP(0.209",5.30mm 宽)
供应商设备封装: 28-SSOP
包装: 带卷 (TR)
输出数目和类型: 2 电压,单极
采样率(每秒): 200k
PCM1792
SLES069B MARCH 2003 REVISED NOVEMBER 2006
www.ti.com
23
Write Register
A master can write to any PCM1792 registers using single or multiple accesses. The master sends a PCM1792 slave
address with a write bit, a register address, and the data. If multiple access is required, the address is that of the
starting register, followed by the data to be transferred. When the data are received properly, the index register is
incremented by 1 automatically. When the index register reaches 0x7F, the next value is 0x0. When undefined
registers are accessed, the PCM1792 does not send an acknowledgement. The Figure 33 is a diagram of the write
operation.
Transmitter
M
MM
S
M
Data Type
St
Slave Address
W
ACK
Reg Address
Write Data 1
S
ACK
S
ACK
M
Sp
M
Write Data 2
S
ACK
S
ACK
M: Master Device
S: Slave Device
St: Start Condition
ACK: Acknowledge
Sp: Stop Condition
W: Write
Figure 33. Write Operation
Read Register
A master can read the PCM1792 register. The value of the register address is stored in an indirect index register in
advance. The master sends a PCM1792 slave address with a read bit after storing the register address. Then the
PCM1792 transfers the data which the index register points to. When the data are transferred during a multiple
access, the index register is incremented by 1 automatically. (When first going into read mode immediately following
a write, the index register is not incremented. The master can read the register that was previously written.) When
the index register reaches 0x7F, the next value is 0x0. The PCM1792 outputs some data when the index register
is 0x10 to 0x1F, even if it is not defined in Table 4. Figure 34 is a diagram of the read operation.
Data
Transmitter
M
MM
S
M
Data Type
St
Slave Address
W
ACK
Reg Address
Slave Address
S
ACK
S
ACK
M
Sp
Slave
M
ACK
S
NACK
M
Sr
M
R
M: Master Device
S: Slave Device
St: Start Condition
Sr: Repeated Start Condition
ACK: Acknowledge
Sp: Stop Condition
NACK: Not Acknowledge
W: Write
R: Read
Figure 34. Read Operation
Noise Suppression
The PCM1792 incorporates noise suppression using the system clock (SCK). However, there must be no more than
two noise spikes in 600 ns. The noise suppression works for SCK frequencies between 8 MHz and 40 MHz in fast
mode. However, it works incorrectly in the following conditions.
Case 1:
1.
t(SCK) > 120 ns (t(SCK): period of SCK)
2.
t(HI) + t(DHD) < t(SCK) × 5
3.
Spike noise exists on the first half of the SCL HIGH pulse.
4.
Spike noise exists on the SDA HIGH pulse just before SDA goes LOW.
SCL
SDA
Noise
When these conditions occur at the same time, the data is recognized as LOW.
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