参数资料
型号: PI7C8140AMAE
厂商: Pericom
文件页数: 71/82页
文件大小: 0K
描述: IC PCI-PCI BRIDGE 2PORT 128-QFP
标准包装: 39
系列: *
应用: *
接口: *
电源电压: *
封装/外壳: 128-BFQFP
供应商设备封装: 128-QFP(14x20)
包装: 管件
安装类型: 表面贴装
PI7C8140A
2-PORT PCI-TO-PCI BRIDGE
Page 73 of 82
March 20, 2007 – Revision 1.01
Bit
Function
Type
Description
5:4
Clock 2 disable
RW
S_CLKOUT[2] (slot 2) Enable
00: enable S_CLKOUT[2]
01: enable S_CLKOUT[2]
10: enable S_CLKOUT[2]
11: disable S_CLKOUT[2] and driven LOW
Reset to 00
7:6
Clock 3 disable
RW
S_CLKOUT[3] (slot 3) Enable
00: enable S_CLKOUT[3]
01: enable S_CLKOUT[3]
10: enable S_CLKOUT[3]
11: disable S_CLKOUT[3] and driven LOW
Reset to 00
8
Reserved
RO
Reserved. Reset to 0
13:9
Reserved
RO
Reserved. Reset to 1Fh
15:14
Reserved
RO
Reserved. Reset to 00
13.2.37 P_SERR# STATUS REGISTER – OFFSET 68h
Bit
Function
Type
Description
16
Address Parity
Error
RWC
1: Signal P_SERR# was asserted because an address parity error was detected on
P or S bus.
Reset to 0
17
Posted Write
Data Parity
Error
RWC
1: Signal P_SERR# was asserted because a posted write data parity error was
detected on the target bus.
Reset to 0
18
Posted Write
Non-delivery
RWC
1: Signal P_SERR# was asserted because the bridge was unable to deliver post
memory write data to the target after 2
24 attempts.
Reset to 0
19
Target Abort
during Posted
Write
RWC
1: Signal P_SERR# was asserted because the bridge received a target abort when
delivering post memory write data.
Reset to 0.
20
Master Abort
during Posted
Write
RWC
1: Signal P_SERR# was asserted because the bridge received a master abort when
attempting to deliver post memory write data
Reset to 0.
21
Delayed Write
Non-delivery
RWC
1: Signal P_SERR# was asserted because the bridge was unable to deliver
delayed write data after 2
24 attempts.
Reset to 0
22
Delayed Read –
No Data from
Target
RWC
1: Signal P_SERR# was asserted because the bridge was unable to read any data
from the target after 2
24 attempts.
Reset to 0.
23
Delayed
Transaction
Master Timeout
RWC
1: Signal P_SERR# was asserted because a master did not repeat a read or write
transaction before master timeout.
Reset to 0.
07-0067
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