参数资料
| 型号： | LTC3816IFE#PBF |
| 厂商： | Linear Technology |
| 文件页数： | 29/44页 |
| 文件大小： | 0K |
| 描述： | IC CONTROLLER S-PHASE 38TSSOP |
| 标准包装： | 50 |
| 应用： | 控制器，Intel IMVP-6，IMVP-6.5? |
| 输入电压： | 4.5 V ~ 36 V |
| 输出数： | 1 |
| 输出电压： | 0.013 V ~ 1.5 V |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 38-TFSOP （0.173"，4.40mm 宽）裸露焊盘 |
| 供应商设备封装： | 38-TSSOP 裸露焊盘 |
| 包装： | 管件 |
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LTC3816
APPLICATIONS INFORMATION
10μA current source pull-up. Placing a resistor between
RFREQ and GND creates a potential given by the follow-
ing equation:
V RFREQ = I RFREQ ? R RFREQ
where I RFREQ = 10μA and allows the oscillator free-running
frequency to be programmed between 210kHz to 580kHz
as shown in Figure 16.
An internal phase-locked loop (PLL) allows the LTC3816
to synchronize the internal oscillator to an external clock.
When there is a clocking signal at the MODE/SYNC pin, the
LTC3816 phase detector adjusts the internal PLL VCO input,
synchronizing the switching frequency to the external clock
frequency, and aligning the TG falling edge to the external
clock’s falling edge. During synchronization, the oscillator
frequency range widens to 120kHz to 650kHz.
For rapid frequency lock-in, the VCO input voltage can be
pre-biased to the desired operating frequency before the
external clock is applied. A resistor connected between
the RFREQ pin and GND can pre-bias the VCO’s input
voltage to the desired potential. Once pre-biased, the PLL
loop only needs to make slight changes to the VCO input
voltage in order to synchronize. The ability to pre-bias the
loop filter allows the PLL to lock-in rapidly.
700
CLKEN#, OVF AND PWRGD
CLKEN# is an open-drain output used to enable the CPU’s
PLL. Upon power-up, this open-drain pull-down is disabled,
and CLKEN# is pulled high by an external resistor. During
the soft-start ramp, when the switcher output is 45mV
from the V BOOT voltage, the controller completes its soft-
start cycle and 75μs later, CLKEN# pulls low to enable the
processor PLL as shown in Figure 2.
At any instant, if the switcher output voltage rises above
the OVF threshold, the PWRGD pulls low, the regulator
output voltage is actively ramped to 0V and PWRGD
remains latched low until either the power is cycled or
VR ON toggles. In the IMVP-6 configuration, the maximum
OVF threshold is 1.7V. In the IMVP-6.5 configuration, the
maximum threshold reduces to 1.55V.
The PWRGD pin is an open-drain output that indicates the
regulator output voltage has stabilized. At start-up, once
the switcher output has settled to its VID potential for more
than 10ms, this open-drain releases and is pulled high by
the external pull-up resistor. It pulls low again if the switcher
output voltage remains outside of the +175mV/–270mV
window around its nominal VID set point for more than
750μs. Once pulled low, the PWRGD state is latched and
the control logic initiates a shutdown sequence. After the
600
500
400
300
200
SYNCHRONIZATION
FREE
RUNNING
100
0
0.3
0.6
0.9
1.2
1.5
1.8
2.1
2.4
V RFREQ (V)
3816 F16
Figure 16. VCO Transfer Curve
3816f
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