参数资料
型号: PIC18F86J16T-I/PT
厂商: Microchip Technology
文件页数: 45/107页
文件大小: 0K
描述: IC PIC MCU FLASH 48KX16 80TQFP
产品培训模块: Asynchronous Stimulus
PIC18 J Series MCU Overview
标准包装: 1,200
系列: PIC® 18F
核心处理器: PIC
芯体尺寸: 8-位
速度: 48MHz
连通性: EBI/EMI,I²C,SPI,UART/USART
外围设备: 欠压检测/复位,LVD,POR,PWM,WDT
输入/输出数: 68
程序存储器容量: 96KB(48K x 16)
程序存储器类型: 闪存
RAM 容量: 3930 x 8
电压 - 电源 (Vcc/Vdd): 2 V ~ 3.6 V
数据转换器: A/D 15x10b
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 80-TQFP
包装: 带卷 (TR)
配用: AC162091-ND - HEADER MPLAB ICD2 18F87J11 64/80
MA180020-ND - MODULE PLUG-IN HPC EXPL 18F87J11
AC164328-ND - MODULE SKT FOR 80TQFP
其它名称: PIC18F86J16T-I/PTTR
PIC18F87J11 FAMILY
DS39778E-page 42
2007-2012 Microchip Technology Inc.
3.4.2
EXTERNAL CLOCK INPUT
(EC MODES)
The EC and ECPLL Oscillator modes require an
external clock source to be connected to the OSC1 pin.
There is no oscillator start-up time required after a
Power-on Reset or after an exit from Sleep mode.
In the EC Oscillator mode, the oscillator frequency,
divided by 4, is available on the OSC2 pin. This signal
may be used for test purposes or to synchronize other
logic. Figure 3-3 shows the pin connections for the EC
Oscillator mode.
FIGURE 3-3:
EXTERNAL CLOCK
INPUT OPERATION
(EC CONFIGURATION)
An external clock source may also be connected to the
OSC1 pin in the HS mode, as shown in Figure 3-4. In
this configuration, the divide-by-4 output on OSC2 is
not available. Current consumption in this configuration
will be somewhat higher than EC mode, as the internal
oscillator’s feedback circuitry will be enabled (in EC
mode, the feedback circuit is disabled).
FIGURE 3-4:
EXTERNAL CLOCK INPUT
OPERATION (HS OSC
CONFIGURATION)
3.4.3
PLL FREQUENCY MULTIPLIER
A Phase Locked Loop (PLL) circuit is provided as an
option for users who want to use a lower frequency oscil-
lator circuit, or to clock the device up to its highest rated
frequency from a crystal oscillator. This may be useful for
customers who are concerned with the External Memory
Interface (EMI) due to high-frequency crystals, or users
who require higher clock speeds from an internal
oscillator.
3.4.3.1
HSPLL and ECPLL Modes
The HSPLL and ECPLL modes provide the ability to
selectively run the device at 4 times the external
oscillating source to produce frequencies up to
40 MHz.
The PLL is enabled by programming the FOSC<2:0>
Configuration bits to either ‘111’ (for ECPLL) or ‘101’ (for
HSPLL). In addition, the PLLEN bit (OSCTUNE<6>)
must also be set. Clearing PLLEN disables the PLL,
regardless of the chosen oscillator configuration. It also
allows additional flexibility for controlling the applica-
tion’s clock speed in software.
FIGURE 3-5:
PLL BLOCK DIAGRAM
3.4.3.2
PLL and INTOSC
The PLL is also available to the internal oscillator block
when the internal oscillator block is configured as the
primary clock source. In this configuration, the PLL is
enabled in software and generates a clock output of up
to 32 MHz. The operation of INTOSC with the PLL is
OSC1/CLKI
OSC2/CLKO
FOSC/4
Clock from
Ext. System
PIC18F87J11
OSC1
OSC2
Open
Clock from
Ext. System
PIC18F87J11
(HS Mode)
MU
X
VCO
Loop
Filter
OSC2
OSC1
PLL Enable (OSCTUNE)
FIN
FOUT
SYSCLK
Phase
Comparator
HSPLL or ECPLL (CONFIG2L)
4
HS or EC
Mode
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