PRELIMINARY
PM4332 TE-32
DATA SHEET
PMC-2011402
ISSUE 1
HIGH DENSITY 32 CHANNEL T1/E1/J1 FRAMER
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR THE INTERNAL USE OF ITS CUSTOMERS
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The E1 framers support detection of various alarm conditions such as loss of
frame, loss of signaling multiframe and loss of CRC multiframe. The E1 framers
also support reception of remote alarm signal, remote multiframe alarm signal,
alarm indication signal, and time slot 16 alarm indication signal.
E1 performance monitoring with accumulation of CRC-4 errors, far end block
errors and framing bit errors is provided. The TE-32 provides a receive HDLC
controller for the detection and termination of messages on the national use bits.
Detection of the 4-bit Sa-bit codewords defined in ITU-T G.704 and ETSI 300-233
is supported. V5.2 link ID signal detection is also supported. An interrupt may be
generated on any change of state of the Sa codewords. An elastic store for slip
buffering and rate adaptation to backplane timing is provided, as is a signaling
extractor that supports signaling debounce, signaling freezing, idle code
substitution, digital milliwatt tone substitution, data inversion, and signaling bit
fixing on a per-channel basis. Receive side data and signaling trunk conditioning
is also provided.
In the egress direction, framing is generated for 32 E1s into SBI add bus. Each
E1 transmitter generates framing for a basic G.704 E1 signal. The signaling
multiframe alignment structure and the CRC multiframe structure may be
optionally inserted. Framing can be optionally disabled. Transmission of the 4-bit
Sa codewords defined in ITU-T G.704 and ETSI 300-233 is supported. PRBS
generation or detection is supported on a framed and unframed E1 basis.
General Operation
The TE-32 can generate a low jitter transmit clock from a variety of clock
references, and also provides jitter attenuation in the receive path. Three jitter
attenuated recovered T1/E1 clocks can be routed outside the TE-32 for network
timing applications.
In synchronous backplane systems, 8 Mbit/s H-MVIP interfaces are provided for
access to 768 DS0 channels, channel associated signaling (CAS) for all 768 DS0
channels and common channel signaling (CCS) for all 32 T1s or 32 E1s (or
combination thereof). The CCS signaling H-MVIP interface is independent of the
DS0 channel and CAS H-MVIP access. The use of any of the H-MVIP interfaces
requires that common clocks and frame pulse be used along with T1 slip buffers.
A Scaleable Bandwidth Interconnect (SBI) high density byte serial system
interface provides higher levels of integration and dense interconnect. The SBI
bus interconnects up to 32 T1s or E1s both synchronously or asynchronously.
The SBI allows transmit timing to be mastered by either the TE-32 or link layer
device connected to the system SBI bus. Error event accumulation is also
provided by the TE-32. Framing bit errors, and far end block errors are
accumulated. Error accumulation continues even while the off-line framers are