DISTINCTIVE CHARACTERISTICS ■ High-Performance Design — Industry-standard write-back cache support — Frequent instructions execute in one clock — 105.6-million bytes/second burst bus at 33 MHz — Flexible write-through and write-back address control — Advanced 0.35-μ CMOS-process technology — Dynamic bus sizing for 8-, 16-, and 32-bit buses — Supports “soft reset” capability ■ High On-Chip Integration — 16-Kbyte unified code and data cache — Floating-point unit — Paged, virtual memory management ■ Enhanced System and Power Management — Stop clock control for reduced power consumption — Industry-standard two-pin System Management Interrupt (SMI) for power management independent of processor operating mode and operating system — Static design with Auto Halt power-down support — Wide range of chipsets supporting SMM avail- able to allow product differentiation ■ Complete 32-Bit Architecture — Address and data buses — All registers — 8-, 16-, and 32-bit data types ■ Standard Features — 3-V core with 5-V tolerant I/O — Available in a 133-MHz version — Binary compatible with all Am486? DX, Am486DX2, and Am486DX4 microprocessors — Wide range of chipsets and support available through the AMD FusionPCSM Program ■ 168-pin PGA package or 208-pin SQFP package ■ IEEE 1149.1 JTAG Boundary-Scan Compatibility ■ Supports Environmental Protection Agency’s Energy Star program — 3-V operation reduces power consumption up to 40% — Energy management capability provides excellent base for energy-efficient design — Works with a variety of energy-efficient, powermanaged devices
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