FEATURES
? VDD=VDDQ=1.5V +/- 0.075V
? Fully differential clock inputs (CK, CK) operation
? Differential Data Strobe (DQS, DQS)
? On chip DLL align DQ, DQS and DQS transition with CK
transition
? DM masks write data-in at the both rising and falling
edges of the data strobe
? All addresses and control inputs except data, data
strobes and data masks latched on the rising edges of
the clock
? Programmable CAS latency 5, 6, 7, 8, 9, 10, 11, 13 and
14 supported
? Programmable additive latency 0, CL-1, and CL-2
supported
? Programmable CAS Write latency (CWL) = 5, 6, 7, 8, 9,
10
? Programmable burst length 4/8 with both nibble
sequential and interleave mode
? BL switch on the fly
? 8banks
? Average Refresh Cycle (Tcase of 0
o
C~ 95
o
C)
- 7.8 μs at 0
o
C ~ 85
o
C
- 3.9 μs at 85
o
C ~ 95
o
C
? JEDEC standard 78ball FBGA(x4/x8), 96ball FBGA(x16
? Driver strength selected by EMRS
? DynamIC On Die Termination supported
? Asynchronous RESET pin supported
? ZQ calibration supported
? TDQS (Termination Data Strobe) supported (x8 only)
? Write Levelization supported
? 8 bit pre-fetch
? This product in compliance with the RoHS directive.
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深圳斯普仑科技有限公司
Shenzhen Spring Technology Co.,Ltd
地址:深圳市福田区振华路122号海外装饰大厦A座211室
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