原装现货 ADC1173 欢迎询价

型号：
ADC1173
厂家：
TI/NS
批号：
13+
封装：
SOP24

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SpecifICation Definitions

ANALOG INPUT BANDWIDTH is a measure of the fre-

quency at which the reconstructed output fundamental drops

3 dB below its low frequency value for a full scale input. The

test is performed with f

IN equal to 100 KHz plus integer mul-

tiples of f

CLK. The input frequency at which the output is ?3

dB relative to the low frequency input signal is the full power

bandwidth.

APERTURE JITTER is the time uncertainty of the sampling

point (t

DS), or the range of variation in the sampling delay.

BOTTOM OFFSET is the difference between the input volt-

age that just causes the output code to transition to the first

code and the negative reference voltage. Bottom offset is

defined as E

OB = VZT -VRB, where VZT is the first code tran-

sition input voltage. Note that this is different from the normal

Zero Scale Error.

DIFFERENTIAL GAIN ERROR is the percentage difference

between the output amplitudes of a high frequency recon-

structed sine wave at two different dc levels.

DIFFERENTIAL NON-LINEARITY (DNL) is the measure of

the maximum deviation from the ideal step size of 1 LSB.

DIFFERENTIAL PHASE ERROR is the difference in the out-

put phase of a reconstructed small signal sine wave at two

different dc levels.

EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE

BITS) is another method of specifying Signal-to-Noise and

Distortion Ratio, or SINAD. ENOB is defined as (SINAD -

1.76) / 6.02 and says that the converter is equivalent to a

perfect ADC of this (ENOB) number of bits.

INTEGRAL NON-LINEARITY (INL) is a measure of the de-

viation of each individual code from a line drawn from zero

scale (1?2LSB below the first code transition) through positive

full scale (1?2LSB above the last code transition). The devia-

tion of any given code from this straight line is measured

from the center of that code value. The end poinnt test

method is used.

OUTPUT DELAY is the time delay after the rising edge of

the input clock before the data update is present at the out-

put pins.

OUTPUT HOLD TIME is the length of time that the output

data is valid after the rise of the input clock.

PIPELINE DELAY (LATENCY) is the number of clock cycles

between initiation of conversion and the availability of that

conversion result at the output. New data is available at ev-

ery clock cycle, but the data lags the conversion by the pipe-

line delay

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