LPC1788FBD144 NXP(恩智浦)

NXP(恩智浦)

LPC1788FBD144  

LQFP144

1. General description The LPC178x/7x is an ARM Cortex-M3 based microcontroller for embedded applications requiring a high level of integration and low power dissipation. The Cortex-M3 is a next generation core that offers better performance than the ARM7 at the same clock rate and other system enhancements such as modernized debug features and a higher level of support BLOCK integration. The Cortex-M3 CPU incorporates a 3-stage pipeline and has a Harvard architecture with separate local instruction and data buses, as well as a third bus with slightly lower performance for peripherals. The Cortex-M3 CPU also includes an internal prefetch unit that supports speculative branches. The LPC178x/7x adds a specialized flash memory accelerator to accomplish optimal performance when executing code from flash. The LPC178x/7x operates at up to 120 MHz CPU frequency. The peripheral complement of the LPC178x/7x includes up to 512 kB of flash program memory, up to 96 kB of SRAM data memory, up to 4032 byte of EEPROM data memory, External Memory Controller (EMC), LCD (LPC178x only), Ethernet, USB Device/Host/OTG, a General Purpose DMA controller, five UARTs, three SSP controllers, three I2C-bus interfaces, one eight-channel, 12-bit ADC, a 10-bit DAC, a Quadrature Encoder Interface, four general purpose timers, two general purpose PWMs with six outputs each and one motor control PWM, an ultra-low power RTC with separate battery supply and event recorder, a windowed watchdog timer, a CRC calculation engine, up to 165 general purpose I/O pins, and more. The pinout of LPC178x/7x is intended to allow pin function compatibility with the LPC24xx and LPC23xx. 2. Features and benefits ? Functional replacement for the LPC23xx and LPC24xx family devices. ? System: ? ARM Cortex-M3 processor, running at frequencies of up to 120 MHz. A Memory Protection Unit (MPU) supporting eight regions is included. ? ARM Cortex-M3 built-in Nested Vectored Interrupt Controller (NVIC). ? Multilayer AHB matrix interconnect provides a separate bus for each AHB master. AHB masters include the CPU,USB, Ethernet, and the General Purpose DMA controller.