- 您现在的位置：买卖IC网 > PDF目录368230 > PSD511B1 PSD5XX/ZPSD5XX FAMILY FIELD-PROGRAMMABLE MICROCONTROLLER PERIPHERALS PDF资料下载
参数资料
| 型号： | PSD511B1 |
| 英文描述： | PSD5XX/ZPSD5XX FAMILY FIELD-PROGRAMMABLE MICROCONTROLLER PERIPHERALS |
| 中文描述： | PSD5XX/ZPSD5XX家庭领域，可编程微控制器外设 |
| 文件页数： | 78/153页 |
| 文件大小： | 1036K |
| 代理商： | PSD511B1 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页当前第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页第101页第102页第103页第104页第105页第106页第107页第108页第109页第110页第111页第112页第113页第114页第115页第116页第117页第118页第119页第120页第121页第122页第123页第124页第125页第126页第127页第128页第129页第130页第131页第132页第133页第134页第135页第136页第137页第138页第139页第140页第141页第142页第143页第144页第145页第146页第147页第148页第149页第150页第151页第152页第153页
PSD5XX Famly
75
9.6.1.5 Time Capture Mode
In the time capture mode, the Counter/Timer is capable of measuring the time
(by counting clock pulses) between events. Figure 39 shows the CTU configuration for
time capture. All the Counter/Timer registers must be cleared during initialization of the
Time Capture mode. Here the Counter is enabled to count via software only. The CTUs
continuously count. A Load/Store pulse triggers the storing of the Counter’s contents into
the associated image register. The image register effectively contains a “snap shot” of the
Counter at the time of the pulse. The CTU Store input is edge-triggered by events, the
events being:
J
Pin Driven.
J
PPLD Macrocell Driven.
J
Software Driven.
A Freeze signal is used to ensure that image data is stable during Microcontroller reads
which is similar to the description of event Counter Microcontroller read accesses. Two
CTUs in time capture mode can be used to capture the rising and the falling edges of a
pulse, the difference of the measurements being the pulse width. The counter continues to
count regardless of the Freeze Acknowledge state.
Note that the time span between two consecutive edges of Time Capture must be greater
than one timer clock cycle in order to be captured.
9.6.1.6 WatchDog Counter/Timer
Counter/Timer-2 can be operated as a WatchDog Timer in both Waveform/Pulse and Event
count/time capture modes. In Event count/time capture mode, Counter/Timer-2 can be
configured only as WatchDog. Figure 40 shows the control signals of the CTU when in
WatchDog mode. When the WatchDog mode is active, CTU2 counts down and at the
terminal count of Counter-2 a WatchDog condition occurs. To avoid the WatchDog from
occurring, a "Write" to the Software Load/Store Bit-2 in the "Software Load/Store Register"
has to take place before the Counter-2 underflows. This action reloads the Counter-2 with
the initial count value in the Image Register-2. Note that this initial count value cannot be
changed after the WatchDog mode is enabled.
The Terminal Count signal of a WatchDog could result in a pulse width that is equal to the
count value loaded into the Image Register of Counter/Timer-2. The active high WatchDog
pulse from Counter 2 is routed through the PPLD, enabling the user to inverse its polarity or
implement any other logic before driving the WatchDog output on a user defined I/O pin.
This signal could be used to drive a RESET pin or trigger a Non-Maskable interrupt on a
processor. Once Counter/Timer-2 is set to the WatchDog mode, it cannot be reconfigured
by software and it can get out of the WatchDog mode only by a RESET.
When the WatchDog is enabled in Power Down and Sleep modes, it remains active
regardless of the state of bit 7 (TMR CLK) in Power Management Mode Register PMMR0.
The WatchDog mode is enabled by setting the WatchDog bit in the global command
register. Setting up the command register for CTU2 is not required except when CTU3 is
configured in pulse mode. In this case, bit 0 of the command register for CTU2 is set to “1”.
Counter/Timer
Operation
(Cont.)
相关PDF资料 |
PDF描述 |
|---|---|
| PSD512B0 | 500V 100kRad Hi-Rel Single N-Channel SEE Hardened MOSFET in a TO-205AF package; A IRHF7430SE with Standard Packaging |
| PSD512B1 | -100V 100kRad Hi-Rel Single P-Channel TID Hardened MOSFET in a SMD-2 package; Similar to IRHNA597160 with optional Total Dose Rating of 300kRads |
| PSD511B1-C-70U | Low Cost Field Programmable Microcontroller Peripherals |
| PSD501B1-C-90JI | Low Cost Field Programmable Microcontroller Peripherals |
| PSD511B1-C-90JI | Low Cost Field Programmable Microcontroller Peripherals |
相关代理商/技术参数 |
参数描述 |
|---|---|
| PSD511B1-12J | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Field-Programmable Peripheral |
| PSD511B1-12JI | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Field-Programmable Peripheral |
| PSD511B1-12LI | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Field-Programmable Peripheral |
| PSD511B1-12U | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Field-Programmable Peripheral |
| PSD511B1-12UI | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Field-Programmable Peripheral |
发布紧急采购，3分钟左右您将得到回复。