- 您现在的位置：买卖IC网 > PDF目录296942 > QL8150-7PT280C (QUICKLOGIC CORP) FPGA, 640 CLBS, 188946 GATES, PBGA280 PDF资料下载
参数资料
| 型号： | QL8150-7PT280C |
| 厂商： | QUICKLOGIC CORP |
| 元件分类： | FPGA |
| 英文描述： | FPGA, 640 CLBS, 188946 GATES, PBGA280 |
| 封装： | 0.80 MM PITCH, LFBGA-280 |
| 文件页数： | 67/96页 |
| 文件大小： | 1607K |
| 代理商： | QL8150-7PT280C |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页当前第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页
2007 QuickLogic Corporation
Eclipse II Family Data Sheet Rev. Q
7
NOTE: Timing numbers in Table 5 represent -8 Worst Case Commercial conditions.
Phase Locked Loop (PLL) Information
Instead of requiring extra components, designers simply need to instantiate one of the pre-configured models
(described in this section). The QuickLogic built-in PLLs support a wider range of frequencies than many other
PLLs. These PLLs also have the ability to support different ranges of frequency multiplications or divisions,
driving the device at a faster or slower rate than the incoming clock frequency. When PLLs are cascaded, the
clock signal must be routed off-chip through the PLLPAD_OUT pin prior to routing into another PLL; internal
routing cannot be used for cascading PLLs.
Figure 6 illustrates a QuickLogic PLL.
Figure 6: PLL Block Diagram
Table 5: ECU Mode Select Criteria
Instruction
Operation
ECU Performancea
, -8 WCC
a. tPD, tSU and tCO do not include routing paths in/out of the ECU block.
S1
S2
S3
t
PD
t
SU
t
CO
0
Multiply
6.6 ns max
0
1
Multiply-Add
8.8 ns max
0
1
0
Accumulateb
b. Internal feedback path in ECU restricts max clk frequency to 238 MHz.
3.9 ns min
1.2 ns max
0
1
Add
3.1 ns max
1
0
Multiply (registered)c
c. B [15:0] set to zero.
9.6 ns min
1.2 ns max
1
0
1
Multiply- Add (registered)
9.6 ns min
1.2 ns max
1
0
Multiply - Accumulate
9.6 ns min
1.2 ns max
1
Add (registered)
3.9 ns min
1.2 ns max
vco
Filter
FIN
FOUT
+
-
1st Quadrant
2nd Quadrant
3rd Quadrant
4th Quadrant
Clock
Tree
Frequency Divide
Frequency Multiply
1
._.
2
._.
4
._.
4
._.
2
._.
1
.._
PLL Bypass
相关PDF资料 |
PDF描述 |
|---|---|
| QL8150-7PT280I | FPGA, 640 CLBS, 188946 GATES, PBGA280 |
| QL8150-7PT280M | FPGA, 640 CLBS, 188946 GATES, PBGA280 |
| QL8150-7PTN280C | FPGA, 640 CLBS, 188946 GATES, PBGA280 |
| QL8150-7PTN280I | FPGA, 640 CLBS, 188946 GATES, PBGA280 |
| QL8150-7PTN280M | FPGA, 640 CLBS, 188946 GATES, PBGA280 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| QL8250 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:LOW POWER FPGA COMBINING PERFORMANCE DENSITY AND EMBEDED RAM |
| QL8250-6PQN208C-5690 | 制造商:QuickLogic Corporation 功能描述: |
| QL8250-6PQN208C-5691 | 制造商:QuickLogic Corporation 功能描述: |
| QL82SD | 制造商:未知厂家 制造商全称:未知厂家 功能描述:10 High Speed Bus LVDS Serial Links bandwidth up to 5 Gbps |
| QL82SD-PB516 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:10 High Speed Bus LVDS Serial Links bandwidth up to 5 Gbps |
发布紧急采购，3分钟左右您将得到回复。