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参数资料
| 型号： | RH80530WZ014256 |
| 厂商： | INTEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 1333 MHz, MICROPROCESSOR, CPGA478 |
| 封装： | MICRO, FLIP CHIP, PGA-478 |
| 文件页数： | 15/91页 |
| 文件大小： | 1142K |
| 代理商： | RH80530WZ014256 |
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22
Datasheet
Electrical Specifications
NOTES:
1. Unless otherwise noted, all specifications in this table are based on latest post-silicon measurements
available at the time of publication.
2. These voltages are targets only. A variable voltage source should exist on systems in the event that a
different voltage is required. See Section 2.4 and Table 3 for more information. The VID bits will set the
typical VCC with the minimum being defined according to current consumption at that voltage.
3. The voltage specification requirements are measured at the system board socket ball with a 100-MHz
bandwidth oscilloscope, 1.5-pF maximum probe capacitance, and 1-M
minimum impedance. The maximum
length of ground wire on the probe should be less than 5 mm. Ensure external noise from the system is not
coupled in the scope probe.
4. Refer to Table 8 to Table 9 and Figure 4 to Figure 5 for the minimum, typical, and maximum VCC (measured
at the system board socket ball) allowed for a given current. The processor should not be subjected to any
VCC and ICC combination wherein VCC exceeds VCC_MAX for a given current. Failure to adhere to this
specification can affect the long term reliability of the processor.
5. VCC_MIN is defined at ICC_MAX.
6. The current specified is also for AutoHALT state.
7. Typical VCC indicates the VID encoded voltage. Voltage supplied must conform to the load line specification
8. The maximum instantaneous current the processor will draw while the thermal control circuit is active as
indicated by the assertion of PROCHOT# is the same as the maximum ICC for the processor.
9. Maximum specifications for ICC Core, ICC Stop-Grant, ICC Sleep, and ICC Deep Sleep are specified at VCC
static Max. derived from the tolerances in Table 8 through Table 9. TJ Max., and under maximum signal
loading conditions.
10.The specification is defined per PLL pin.
11.The voltage response to a processor current load step (transient) must stay within the transient voltage
tolerance window. The voltage surge or droop response measured in this window is typically on the order of
several hundred nanoseconds to several microseconds. The Transient Voltage Tolerance Window is defined
as follows:
Case a) Load Current Step Up: e.g., from Icc = I_leakage to Icc = Icc_max. Allowable Vcc_min is defined as
minimum transient voltage at Icc = Icc_max for a period of time lasting several hundred nanoseconds to
several microseconds after the transient event.
Case b) Load Current Step Down: e.g., form Icc = Icc_max to Icc = I_leakage. Allowable Vcc_max is defined
Table 7.
Voltage and Current Specifications
Symbol
Parameter
Min
Typ
Max
Unit
Notes1
VCC
VCC for core logic
1.30
V
2, 3, 4, 5, 7, 8,11
VCCVID
VID supply voltage
-5%
1.20
+10%
V
2, 12
ICC
Current for VCC at core frequency
2.50 GHz & 1.30 V
2.40 GHz & 1.30 V
2.20 GHz & 1.30 V
2.00 GHz & 1.30 V
1.80 GHz & 1.30 V
1.70 GHz & 1.30 V
1.60 GHz & 1.30 V
1.50 GHz & 1.30 V
1.40 GHz & 1.30 V
1.20 GHz & 1.30 V13
37.7
36.7
34.5
33.3
31.0
29.9
28.7
27.5
26.3
23.0
A
4, 5, 8, 9
IVCCVID
Current for VID supply
300
mA
ISGNT, ISLP
ICC Stop-Grant and ICCSleep at
1.30 V (for > 2.0 GHz)
1.30 V (for <= 2.0 GHz)
10.5
10.1
A
6, 9
IDSLP
ICC Deep Sleep at
1.30 V
9.0
A
9
ITCC
ICC TCC active
ICC
A8
ICC PLL
ICC for PLL pins
60
mA
10
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相关代理商/技术参数 |
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