19 UNIVERSAL SERIAL INTERFACE (USI) [S1C17564]
S1C17554/564 TECHNICAL MANUAL
Seiko Epson Corporation
19-19
(4) When a stop condition is received
If the ISSTA[2:0] value read during data reception is 0x1, the I2C master device has generated a stop condi-
tion (see Figure 19.5.3.6). In this case, abort data reception.
Clock stretch function
While data is being sent/received, this I2C slave generates a clock stretch status by pulling down the SCL line to
low to make a wait request to the master device after an ACK is sent/received until the following data transfer is
started.
Receive Errors
19.6
In UART mode, three different receive errors (overrun error, framing error, and parity error) may be detected while
receiving data. In SPI master and I2C modes, overrun errors may be detected while receiving data.
Since receive errors are interrupt causes, they can be processed by generating interrupts. For more information on
interrupt control, see Section 19.7.
Overrun error (all interface modes)
If data is received before the previously received data in the receive data buffer has not been read, the receive
data buffer is overwritten and an overrun error occurs. When an overrun error occurs, the overrun error flag for
the current interface mode is set to 1.
Overrun error flags: UOEIF/USI_UIFx register (UART mode)
SEIF/USI_SIFx register
(SPI master mode)
IMEIF/USI_IMIFx register (I2C master mode)
ISEIF/USI_ISIFx register
(I2C slave mode)
The receiving operation continues even if this error occurs. The overrun error flag is reset to 0 by writing 1.
Framing error (UART mode only)
If the stop bit is received as 0 in UART mode, the UART controller determines loss of sync and a framing error
occurs. If the stop bit is configured to two bits, only the first bit is checked.
The framing error flag (USEIF/USI_UIFx register) is set to 1 if this error occurs. The received data is still trans-
ferred to the receive data buffer if this error occurs and the receiving operation continues, but the data cannot be
guaranteed, even if no framing error occurs for subsequent data receiving. The framing error flag is reset to 0
by writing 1.
Parity error (UART mode only)
If UPREN/USI_UCFGx register has been set to 1 (parity enabled), data received is checked for parity in UART
mode. Data received in the shift register is checked for parity when sent to the receive data buffer. The match-
ing is checked against the UPMD/USI_UCFGx register setting (odd or even parity). If the result is a non-match,
a parity error is issued, and the parity error flag (UPEIF/USI_UIFx register) is set to 1. Even if this error occurs,
the data received is sent to the receive data buffer, and the receiving operation continues. However, the received
data cannot be guaranteed if a parity error occurs. The UPEIF flag is reset to 0 by writing 1.
USI Interrupts
19.7
This section describes the USI interrupts generated in each interface mode.
For more information on interrupt processing, see the “Interrupt Controller (ITC)” chapter.
Each USI channel outputs one interrupt signal (two signals for two channels) shared by the all interrupt causes to
the interrupt controller (ITC). Inspect the interrupt flags available in each mode to determine the interrupt cause oc-
curred.