APPENDIX A LIST OF I/O REGISTERS
AP-A-10
Seiko Epson Corporation
S1C17554/564 TECHNICAL MANUAL
Register name Address
Bit
Name
Function
Setting
Init. R/W
Remarks
T16F Ch.1
Control Register
(T16F_CTL1)
0x4286
(16 bits)
D15–12 –
reserved
–
0 when being read.
D11–8 TFMD[3:0] Fine mode setup
0x0 to 0xf
0x0 R/W Set a number of times
to insert delay into a
16-underflow period.
D7–5 –
reserved
–
0 when being read.
D4
TRMD
Count mode select
1 One shot
0 Repeat
0
R/W
D3–2 –
reserved
–
0 when being read.
D1
PRESER
Timer reset
1 Reset
0 Ignored
0
W
D0
PRUN
Timer run/stop control
1 Run
0 Stop
0
R/W
T16F Ch.1
Interrupt
Control Register
(T16F_INT1)
0x4288
(16 bits)
D15–9 –
reserved
–
0 when being read.
D8
T16FIE
T16F interrupt enable
1 Enable
0 Disable
0
R/W
D7–1 –
reserved
–
0 when being read.
D0
T16FIF
T16F interrupt flag
1 Cause of
interrupt
occurred
0 Cause of
interrupt not
occurred
0
R/W Reset by writing 1.
0x4306–0x431c
Interrupt Controller
Register name Address
Bit
Name
Function
Setting
Init. R/W
Remarks
Interrupt Level
Setup Register 0
(ITC_LV0)
0x4306
(16 bits)
D15–11 –
reserved
–
0 when being read.
D10–8 ILV1[2:0]
P1 interrupt level
0 to 7
0x0 R/W
D7–3 –
reserved
–
0 when being read.
D2–0 ILV0[2:0]
P0 interrupt level
0 to 7
0x0 R/W
Interrupt Level
Setup Register 1
(ITC_LV1)
0x4308
(16 bits)
D15–11 –
reserved
–
0 when being read.
D10–8 ILV3[2:0]
CT interrupt level
0 to 7
0x0 R/W
D7–3 –
reserved
–
0 when being read.
D2–0 ILV2[2:0]
SWT interrupt level
0 to 7
0x0 R/W
Interrupt Level
Setup Register 2
(ITC_LV2)
0x430a
(16 bits)
D15–1 –
reserved
–
0 when being read.
D10–8 ILV5[2:0]
P4 interrupt level
0 to 7
0x0 R/W
D7–3 –
reserved
–
0 when being read.
D2–0 ILV4[2:0]
T16A Ch.2 interrupt level
0 to 7
0x0 R/W
Interrupt Level
Setup Register 3
(ITC_LV3)
0x430c
(16 bits)
D15–11 –
reserved
–
0 when being read.
D10–8 ILV7[2:0]
T16A Ch.0 interrupt level
0 to 7
0x0 R/W
D7–3 –
reserved
–
0 when being read.
D2–0 ILV6[2:0]
SPI Ch.2 interrupt level
0 to 7
0x0 R/W
Interrupt Level
Setup Register 4
(ITC_LV4)
0x430e
(16 bits)
D15–11 –
reserved
–
0 when being read.
D10–8 ILV9[2:0]
T16 Ch.0 interrupt level
0 to 7
0x0 R/W
D7–3 –
reserved
–
0 when being read.
D2–0 ILV8[2:0]
T16F Ch.0 & 1/USI Ch.0 & 1 inter-
rupt level
0 to 7
0x0 R/W
Interrupt Level
Setup Register 5
(ITC_LV5)
0x4310
(16 bits)
D15–11 –
reserved
–
0 when being read.
D10–8 ILV11[2:0]
T16 Ch.2/T16A Ch.3 interrupt
level
0 to 7
0x0 R/W
D7–3 –
reserved
–
0 when being read.
D2–0 ILV10[2:0]
T16 Ch.1 interrupt level
0 to 7
0x0 R/W
Interrupt Level
Setup Register 6
(ITC_LV6)
0x4312
(16 bits)
D15–11 –
reserved
–
0 when being read.
D10–8 ILV13[2:0]
UART Ch.1 interrupt level
0 to 7
0x0 R/W
D7–3 –
reserved
–
0 when being read.
D2–0 ILV12[2:0]
UART Ch.0 interrupt level
0 to 7
0x0 R/W
Interrupt Level
Setup Register 7
(ITC_LV7)
0x4314
(16 bits)
D15–11 –
reserved
–
0 when being read.
D10–8 ILV15[2:0]
I2CM interrupt level
0 to 7
0x0 R/W
D7–3 –
reserved
–
0 when being read.
D2–0 ILV14[2:0]
SPI Ch.0 interrupt level
0 to 7
0x0 R/W
Interrupt Level
Setup Register 8
(ITC_LV8)
0x4316
(16 bits)
D15–11 –
reserved
–
0 when being read.
D10–8 ILV17[2:0]
T16A Ch.1 interrupt level
0 to 7
0x0 R/W
D7–3 –
reserved
–
0 when being read.
D2–0 ILV16[2:0]
REMC/SPI Ch.1 interrupt level
0 to 7
0x0 R/W
Interrupt Level
Setup Register 9
(ITC_LV9)
0x4318
(16 bits)
D15–11 –
reserved
–
0 when being read.
D10–8 ILV19[2:0]
P5 interrupt level
0 to 7
0x0 R/W
D7–3 –
reserved
–
0 when being read.
D2–0 ILV18[2:0]
ADC10 interrupt level
0 to 7
0x0 R/W
Interrupt Level
Setup Register
10
(ITC_LV10)
0x431a
(16 bits)
D15–11 –
reserved
–
0 when being read.
D10–8 ILV21[2:0]
P3 interrupt level
0 to 7
0x0 R/W
D7–3 –
reserved
–
0 when being read.
D2–0 ILV20[2:0]
P2 interrupt level
0 to 7
0x0 R/W
Interrupt Level
Setup Register
11
(ITC_LV11)
0x431c
(16 bits)
D15–3 –
reserved
–
0 when being read.
D2–0 ILV22[2:0]
I2CS interrupt level
0 to 7
0x0 R/W