11 16-BIT PWM TIMERS (T16A)
11-16
Seiko Epson Corporation
S1C17554/564 TECHNICAL MANUAL
T16A Comparator/Capture Ch.x Control Registers (T16A_CCCTLx)
Register name Address
Bit
Name
Function
Setting
Init. R/W
Remarks
T16A
Comparator/
Capture Ch.x
Control Register
(T16A_CCCTLx)
0x5404
0x5424
0x5444
0x5464
(16 bits)
D15–14 CAPBTRG
[1:0]
Capture B trigger select
CAPBTRG[1:0] Trigger edge
0x0 R/W
0x3
0x2
0x1
0x0
↑ and ↓
↓
↑
None
D13–12 TOUTBMD
[1:0]
TOUT B mode select
TOUTBMD[1:0]
Mode
0x0 R/W
0x3
0x2
0x1
0x0
cmp B:
↑ or ↓
cmp A:
↑ or ↓
cmp A:
↑, B: ↓
Off
D11–10 –
reserved
–
0 when being read.
D9
TOUTBINV TOUT B invert
1 Invert
0 Normal
0
R/W
D8
CCBMD
T16A_CCB register mode select
1 Capture
0 Comparator
0
R/W
D7–6 CAPATRG
[1:0]
Capture A trigger select
CAPATRG[1:0] Trigger edge
0x0 R/W
0x3
0x2
0x1
0x0
↑ and ↓
↓
↑
None
D5–4 TOUTAMD
[1:0]
TOUT A mode select
TOUTAMD[1:0]
Mode
0x0 R/W
0x3
0x2
0x1
0x0
cmp B:
↑ or ↓
cmp A:
↑ or ↓
cmp A:
↑, B: ↓
Off
D3–2 –
reserved
–
0 when being read.
D1
TOUTAINV TOUT A invert
1 Invert
0 Normal
0
R/W
D0
CCAMD
T16A_CCA register mode select
1 Capture
0 Comparator
0
R/W
D[15:14] CAPBTRG[1:0]: Capture B Trigger Select Bits
Selects the trigger edge(s) of the external signal (CAP1/3/5/7) at which the counter value is captured in
the capture B register.
8.5 Capture B Trigger Edge Selection
Table 11.
CAPBTRG[1:0]
Trigger edge
0x3
Falling edge and rising edge
0x2
Falling edge
0x1
Rising edge
0x0
Not triggered
(Default: 0x0)
CAPBTRG[1:0] are control bits for capture mode and are ineffective in comparator mode.
D[13:12] TOUTBMD[1:0]: TOUT B Mode Select Bits
Configures how the TOUT B signal waveform (TOUT1/3/5/7 output) is changed by the compare A and
compare B signals. These bits are also used to turn the TOUT B output On and Off.
8.6 TOUT B Generation Mode
Table 11.
TOUTBMD[1:0]
When compare A occurs When compare B occurs
0x3
No change
Toggle
0x2
Toggle
No change
0x1
Rise
Fall
0x0
Disable output
(Default: 0x0)
TOUTBMD[1:0] are control bits for comparator mode and are ineffective in capture mode.
D[11:10] Reserved
D9
TOUTBINV: TOUT B Invert Bit
Selects the TOUT B signal (TOUT1/3/5/7 output) polarity.
1 (R/W): Inverted (active Low)
0 (R/W): Normal (active High) (default)
Writing 1 to TOUTBINV generates an active Low signal (Off level = High) for the TOUT B output.
When TOUTBINV is 0, an active High signal (Off level = Low) is generated.
TOUTBINV is a control bit for comparator mode and is ineffective in capture mode.