APPENDIX A LIST OF I/O REGISTERS
AP-A-14
Seiko Epson Corporation
S1C17554/564 TECHNICAL MANUAL
0x5060–0x5081
Clock Generator
Register name Address
Bit
Name
Function
Setting
Init. R/W
Remarks
Clock Source
Select Register
(CLG_SRC)
S1C17554
0x5060
(8 bits)
D7–2 –
reserved
–
0 when being read.
D1–0 CLKSRC[1:0] System clock source select
CLKSRC[1:0]
Clock source
0x2 R/W
0x3
0x2
0x1
0x0
reserved
OSC3
OSC1
reserved
Clock Source
Select Register
(CLG_SRC)
S1C17564
0x5060
(8 bits)
D7–2 –
reserved
–
0 when being read.
D1–0 CLKSRC[1:0] System clock source select
CLKSRC[1:0]
Clock source
0x0 R/W
0x3
0x2
0x1
0x0
reserved
OSC3
OSC1
IOSC
Oscillation
Control Register
(CLG_CTL)
S1C17554
0x5061
(8 bits)
D7–6 –
reserved
–
0 when being read.
D5–4 OSC3WT[1:0] OSC3 wait cycle select
OSC3WT[1:0]
Wait cycle
0x0 R/W
0x3
0x2
0x1
0x0
128 cycles
256 cycles
512 cycles
1024 cycles
D3–2 –
reserved
–
0 when being read.
D1
OSC1EN
OSC1 enable
1 Enable
0 Disable
0
R/W
D0
OSC3EN
OSC3 enable
1 Enable
0 Disable
1
R/W
Oscillation
Control Register
(CLG_CTL)
S1C17564
0x5061
(8 bits)
D7–6 IOSCWT[1:0] IOSC wait cycle select
IOSCWT[1:0]
Wait cycle
0x0 R/W
0x3
0x2
0x1
0x0
8 cycles
16 cycles
32 cycles
64 cycles
D5–4 OSC3WT[1:0] OSC3 wait cycle select
OSC3WT[1:0]
Wait cycle
0x0 R/W
0x3
0x2
0x1
0x0
128 cycles
256 cycles
512 cycles
1024 cycles
D3
–
reserved
–
0 when being read.
D2
IOSCEN
IOSC enable
1 Enable
0 Disable
1
R/W
D1
OSC1EN
OSC1 enable
1 Enable
0 Disable
0
R/W
D0
OSC3EN
OSC3 enable
1 Enable
0 Disable
0
R/W
Noise Filter
Enable Register
(CLG_NFEN)
0x5062
(8 bits)
D7–6 –
reserved
–
0 when being read.
D5
OSC1WCE OSC1 wait cycle enable
1 Enable
0 Disable
1
R/W
D4
OSC3WCE OSC3 wait cycle enable
1 Enable
0 Disable
1
R/W
D3–0 –
reserved
–
0 when being read.
FOUTA Control
Register
(CLG_FOUTA)
S1C17554
0x5064
(8 bits)
D7–6 –
reserved
–
0 when being read.
D5–4 FOUTAD
[1:0]
FOUTA clock division ratio select
FOUTAD[1:0]
Division ratio
0x0 R/W When the clock
source is OSC3
0x3
0x2
0x1
0x0
reserved
1/4
1/2
1/1
D3–2 FOUTASRC
[1:0]
FOUTA clock source select
FOUTASRC[1:0] Clock source
0x0 R/W
0x3
0x2
0x1
0x0
reserved
OSC3
OSC1
reserved
D1
–
reserved
–
0 when being read.
D0
FOUTAE
FOUTA output enable
1 Enable
0 Disable
0
R/W
FOUTA Control
Register
(CLG_FOUTA)
S1C17564
0x5064
(8 bits)
D7–6 –
reserved
–
0 when being read.
D5–4 FOUTAD
[1:0]
FOUTA clock division ratio select
FOUTAD[1:0]
Division ratio
0x0 R/W When the clock
source is IOSC or
OSC3
0x3
0x2
0x1
0x0
reserved
1/4
1/2
1/1
D3–2 FOUTASRC
[1:0]
FOUTA clock source select
FOUTASRC[1:0] Clock source
0x0 R/W
0x3
0x2
0x1
0x0
reserved
OSC3
OSC1
IOSC
D1
–
reserved
–
0 when being read.
D0
FOUTAE
FOUTA output enable
1 Enable
0 Disable
0
R/W