APPENDIX A LIST OF I/O REGISTERS
S1C17554/564 TECHNICAL MANUAL
Seiko Epson Corporation
AP-A-21
Register name Address
Bit
Name
Function
Setting
Init. R/W
Remarks
P2 Port Input
Enable Register
(P2_IEN)
0x522a
(8 bits)
D7–0 P2IEN[7:0] P2[7:0] port input enable
1 Enable
0 Disable
0xff R/W
P3 Port Input
Data Register
(P3_IN)
0x5230
(8 bits)
D7–0 P3IN[7:0]
P3[7:0] port input data
1 1 (H)
0 0 (L)
×
R
P3 Port Output
Data Register
(P3_OUT)
0x5231
(8 bits)
D7–0 P3OUT[7:0] P3[7:0] port output data
1 1 (H)
0 0 (L)
0
R/W
P3 Port
Output Enable
Register
(P3_OEN)
0x5232
(8 bits)
D7–0 P3OEN[7:0] P3[7:0] port output enable
1 Enable
0 Disable
0
R/W
P3 Port Pull-up
Control Register
(P3_PU)
0x5233
(8 bits)
D7–0 P3PU[7:0]
P3[7:0] port pull-up enable
1 Enable
0 Disable
1
(0xff)
R/W
P3 Port
Interrupt Mask
Register
(P3_IMSK)
0x5235
(8 bits)
D7–0 P3IE[7:0]
P3[7:0] port interrupt enable
1 Enable
0 Disable
0
R/W
P3 Port
Interrupt Edge
Select Register
(P3_EDGE)
0x5236
(8 bits)
D7–0 P3EDGE[7:0] P3[7:0] port interrupt edge select
1 Falling edge 0 Rising edge
0
R/W
P3 Port
Interrupt Flag
Register
(P3_IFLG)
0x5237
(8 bits)
D7–0 P3IF[7:0]
P3[7:0] port interrupt flag
1 Cause of
interrupt
occurred
0 Cause of
interrupt not
occurred
0
R/W Reset by writing 1.
P3 Port
Chattering
Filter Control
Register
(P3_CHAT)
0x5238
(8 bits)
D7
–
reserved
–
0 when being read.
D6–4 P3CF2[2:0] P3[7:4] chattering filter time
P3CF2[2:0]
Filter time
0
R/W
0x7
0x6
0x5
0x4
0x3
0x2
0x1
0x0
16384/fPCLK
8192/fPCLK
4096/fPCLK
2048/fPCLK
1024/fPCLK
512/fPCLK
256/fPCLK
None
0x0 R/W
D3
–
reserved
–
0 when being read.
D2–0 P3CF1[2:0] P3[3:0] chattering filter time
P3CF1[2:0]
Filter time
0x0 R/W
0x7
0x6
0x5
0x4
0x3
0x2
0x1
0x0
16384/fPCLK
8192/fPCLK
4096/fPCLK
2048/fPCLK
1024/fPCLK
512/fPCLK
256/fPCLK
None
P3 Port Input
Enable Register
(P3_IEN)
0x523a
(8 bits)
D7–0 P3IEN[7:0] P3[7:0] port input enable
1 Enable
0 Disable
0xff R/W
P4 Port Input
Data Register
(P4_IN)
0x5240
(8 bits)
D7–6 –
reserved
–
0 when being read.
D5–0 P4IN[5:0]
P4[5:0] port input data
1 1 (H)
0 0 (L)
×
R
P4 Port Output
Data Register
(P4_OUT)
0x5241
(8 bits)
D7–6 –
reserved
–
0 when being read.
D5–0 P4OUT[5:0] P4[5:0] port output data
1 1 (H)
0 0 (L)
0
R/W
P4 Port
Output Enable
Register
(P4_OEN)
0x5242
(8 bits)
D7–6 –
reserved
–
0 when being read.
D5–0 P4OEN[5:0] P4[5:0] port output enable
1 Enable
0 Disable
0
R/W
P4 Port Pull-up
Control Register
(P4_PU)
0x5243
(8 bits)
D7–6 –
reserved
–
0 when being read.
D5–0 P4PU[5:0]
P4[5:0] port pull-up enable
1 Enable
0 Disable
1
(0x2f)
R/W
P4 Port
Interrupt Mask
Register
(P4_IMSK)
0x5245
(8 bits)
D7–6 –
reserved
–
0 when being read.
D5–0 P4IE[5:0]
P4[5:0] port interrupt enable
1 Enable
0 Disable
0
R/W
P4 Port
Interrupt Edge
Select Register
(P4_EDGE)
0x5246
(8 bits)
D7–6 –
reserved
–
0 when being read.
D5–0 P4EDGE[5:0] P4[5:0] port interrupt edge select
1 Falling edge 0 Rising edge
0
R/W
P4 Port
Interrupt Flag
Register
(P4_IFLG)
0x5247
(8 bits)
D7–6 –
reserved
–
0 when being read.
D5–0 P4IF[5:0]
P4[5:0] port interrupt flag
1 Cause of
interrupt
occurred
0 Cause of
interrupt not
occurred
0
R/W Reset by writing 1.