3 MEMORY MAP, BUS CONTROL
3-2
Seiko Epson Corporation
S1C17554/564 TECHNICAL MANUAL
1.1 Number of Bus Accesses
Table 3.
Device size
CPU access size
Number of bus accesses
8 bits
1
16 bits
2
32 bits*
4
16 bits
8 bits
1
16 bits
1
32 bits*
2
32 bits
8 bits
1
16 bits
1
32 bits*
1
* Handling the eight high-order bits during 32-bit accesses
The size of the S1C17 Core general-purpose registers is 24 bits.
During writing, the eight high-order bits are written as 0. During reading from a memory, the eight high-order
bits are ignored. However, the stack operation in an interrupt handling reads/writes 32-bit data that consists of the
PSR value as the high-order 8 bits and the return address as the low order 24 bits.
For more information, refer to the “S1C17 Core Manual.”
Restrictions on Access Size
3.1.1
The peripheral modules can be accessed with an 8-bit, 16-bit, or 32-bit instruction. However, reading for an unnec-
essary register may change the peripheral module status and it may cause a problem. Therefore, use the appropriate
instructions according to the device size.
Restrictions on Instruction Execution Cycles
3.1.2
An instruction fetch and a data access are not performed simultaneously under one of the conditions listed below.
This prolongs the instruction fetch cycle for the number of data area bus cycles.
When the S1C17554/564 executes the instruction stored in the Flash area and accesses data in the Flash area
When the S1C17554/564 executes the instruction stored in the internal RAM area and accesses data in the inter-
nal RAM area
Flash Area
3.2
Embedded Flash Memory
3.2.1
The 128K-byte area from address 0x8000 to address 0x27fff contains a Flash memory (4K bytes
× 32 sectors) for
storing application programs and data. Address 0x8000 is defined as the vector table base address, therefore a vec-
tor table (see “Vector Table” in the “Interrupt Controller (ITC)” chapter) must be placed from the beginning of the
area. The vector table base address can be modified with the MISC_TTBRL/MISC_TTBRH registers.
Flash Programming
3.2.2
The S1C17554/564 supports on-board programming of the Flash memory, it makes it possible to program the Flash
memory with the application programs/data by using the debugger through an ICDmini. The Flash memory sup-
ports sector erase method.
For the Flash programming using the debugger, see the “S5U1C17001C Manual” included in the S1C17 Family
C Compiler Package. For the self-programming controlled by the user program, see the “Self-Programming (FLS)
Application Notes” for the S1C17554/564.