6 INTERRUPT CONTROLLER (ITC)
6-2
Seiko Epson Corporation
S1C17554/564 TECHNICAL MANUAL
S1C17 Core
Interrupt controller
Watchdog timer
Interrupt
request
Interrupt
level
Vector
number
Debug signal
Reset signal
Interrupt
request
NMI
Interrupt level
Interrupt
control
Vector number
Interrupt level
Vector number
Interrupt
request
Peripheral module
Interrupt enable
Cause of interrupt 1
Interrupt enable
Cause of interrupt n
Interrupt flag
Peripheral module
Interrupt enable
Cause of interrupt 1
Interrupt enable
Cause of interrupt n
Interrupt flag
1.1 Interrupt System
Figure 6.
Vector Table
6.2
The vector table contains the vectors to the interrupt handler routines (handler routine start address) that will be
read by the S1C17 Core to execute the handler when an interrupt occurs.
Table 6.2.1 shows the vector table of the S1C17554/564.
2.1 Vector Table
Table 6.
Vector No.
Software interrupt No.
Vector address
Hardware interrupt name
Cause of hardware interrupt
Priority
0 (0x00)
TTBR + 0x00
Reset
Low input to the #RESET pin
Watchdog timer overow *2
1
1 (0x01)
TTBR + 0x04
Address misaligned interrupt
Memory access instruction
2
–
(0xfffc00)
Debugging interrupt
brk
instruction, etc.
3
2 (0x02)
TTBR + 0x08
NMI
Watchdog timer overow *2
4
3 (0x03)
TTBR + 0x0c
Reserved for C compiler
–
4 (0x04)
TTBR + 0x10
P0 port interrupt
P00–P03 port inputs
High *1
5 (0x05)
TTBR + 0x14
P1 port interrupt
P10–P17 port inputs
↑
6 (0x06)
TTBR + 0x18
Stopwatch timer interrupt
100 Hz timer signal
10 Hz timer signal
1 Hz timer signal
7 (0x07)
TTBR + 0x1c
Clock timer interrupt
32 Hz timer signal
8 Hz timer signal
2 Hz timer signal
1 Hz timer signal
8 (0x08)
TTBR + 0x20
16-bit PWM timer Ch.2 interrupt
Compare A/B
Capture A/B
Capture A/B overwrite
9 (0x09)
TTBR + 0x24
P4 port interrupt
P40–P45 port inputs
10 (0x0a)
TTBR + 0x28
SPI Ch.2 interrupt
Transmit buffer empty
Receive buffer full
11 (0x0b)
TTBR + 0x2c
16-bit PWM timer Ch.0 interrupt
Compare A/B
Capture A/B
Capture A/B overwrite
12 (0x0c)
TTBR + 0x30
Fine mode 16-bit timer Ch.0 and
Ch.1 interrupt
Ch.0 underow
Ch.1 underow
USI Ch.0 and Ch.1 interrupt
Ch.0 transmit buffer empty
Ch.0 receive buffer full
Ch.0 receive error
Ch.1 transmit buffer empty
Ch.1 receive buffer full
Ch.1 receive error
13 (0x0d)
TTBR + 0x34
16-bit timer Ch.0 interrupt
Timer underow