6 INTERRUPT CONTROLLER (ITC)
S1C17554/564 TECHNICAL MANUAL
Seiko Epson Corporation
6-7
Interrupt Level Setup Register x (ITC_LVx)
Register name Address
Bit
Name
Function
Setting
Init. R/W
Remarks
Interrupt Level
Setup Register x
(ITC_LVx)
0x4306
|
0x431c
(16 bits)
D15–11 –
reserved
–
0 when being read.
D10–8 ILVn[2:0]
INTn (1, 3, ... 21) interrupt level
0 to 7
0x0 R/W
D7–3 –
reserved
–
0 when being read.
D2–0 ILVn[2:0]
INTn (0, 2, ... 22) interrupt level
0 to 7
0x0 R/W
D[15:11], D[7:3]
Reserved
D[10:8], D[2:0]
ILVn[2:0]: INTn Interrupt Level Bits (n = 0–22)
Sets the interrupt level (0 to 7) of each interrupt. (Default: 0x0)
The S1C17 Core does not accept interrupts with a level set lower than the PSR IL value.
The ITC uses the interrupt level when multiple interrupt requests occur simultaneously.
If multiple interrupt requests enabled by the interrupt enable bit occur simultaneously, the ITC sends the
interrupt request with the highest level set by the ITC_LVx registers (0x4306 to 0x431c) to the S1C17
Core.
If multiple interrupt requests with the same interrupt level occur simultaneously, the interrupt with the
lowest vector number is processed first.
The other interrupts are held until all interrupts of higher priority have been accepted by the S1C17
Core.
If an interrupt requests of higher priority occurs while the ITC outputs an interrupt request signal to the
S1C17 Core (before acceptance by the S1C17 Core), the ITC alters the vector number and interrupt
level signals to the setting details of the most recent interrupt. The immediately preceding interrupt is
held.
7.2 Interrupt Level Bits
Table 6.
Register
Bit
Interrupt
ITC_LV0(0x4306)
ILV0[2:0] (D[2:0])
P0 port interrupt
ILV1[2:0] (D[10:8])
P1 port interrupt
ITC_LV1(0x4308)
ILV2[2:0] (D[2:0])
Stopwatch timer interrupt
ILV3[2:0] (D[10:8])
Clock timer interrupt
ITC_LV2(0x430a)
ILV4[2:0] (D[2:0])
16-bit PWM timer Ch.2 interrupt
ILV5[2:0] (D[10:8])
P4 port interrupt
ITC_LV3(0x430c)
ILV6[2:0] (D[2:0])
SPI Ch.2 interrupt
ILV7[2:0] (D[10:8])
16-bit PWM timer Ch.0 interrupt
ITC_LV4(0x430e)
ILV8[2:0] (D[2:0])
Fine mode 16-bit timer Ch.0 & Ch.1 interrupt /
USI Ch.0 & Ch.1 interrupt
ILV9[2:0] (D[10:8])
16-bit timer Ch.0 interrupt
ITC_LV5(0x4310)
ILV10[2:0] (D[2:0])
16-bit timer Ch.1 interrupt
ILV11[2:0] (D[10:8])
16-bit timer Ch.2 interrupt /
16-bit PWM timer Ch.3 interrupt
ITC_LV6(0x4312)
ILV12[2:0] (D[2:0])
UART Ch.0 interrupt
ILV13[2:0] (D[10:8])
UART Ch.1 interrupt
ITC_LV7(0x4314)
ILV14[2:0] (D[2:0])
SPI Ch.0 interrupt
ILV15[2:0] (D[10:8])
I2C master interrupt
ITC_LV8(0x4316)
ILV16[2:0] (D[2:0])
IR remote controller interrupt /
SPI Ch.1 interrupt
ILV17[2:0] (D[10:8])
16-bit PWM timer Ch.1 interrupt
ITC_LV9(0x4318)
ILV18[2:0] (D[2:0])
A/D converter interrupt
ILV19[2:0] (D[10:8])
P5 port interrupt
ITC_LV10(0x431a) ILV20[2:0] (D[2:0])
P2 port interrupt
ILV21[2:0] (D[10:8])
P3 port interrupt
ITC_LV11(0x431c) ILV22[2:0] (D[2:0])
I2C slave interrupt
(ILV23[2:0] (D[10:8])) Reserved