7 CLOCK GENERATOR (CLG)
7-6
Seiko Epson Corporation
S1C17554/564 TECHNICAL MANUAL
3.3.2 IOSC Oscillation Stabilization Wait Time Settings
Table 7.
IOSCWT[1:0]
Oscillation stabilization wait time
0x3
8 cycles
0x2
16 cycles
0x1
32 cycles
0x0
64 cycles
(Default: 0x0)
This is set to 64 cycles (IOSC clock) after an initial reset. This means the CPU can start operating when the
CPU operation start time at initial reset indicated below (at a maximum) has elapsed after the reset state is can-
celed. For the oscillation start time, see the “Electrical Characteristics” chapter.
CPU operation start time at initial reset
≤ IOSC oscillation start time (max.) + IOSC oscillation stabilization
wait time (64 cycles)
When the system clock is switched to IOSC immediately after turning the IOSC oscillator on, the IOSC clock
is supplied to the system after the IOSC clock system supply wait time indicated below (at a maximum) has
elapsed. If the power supply voltage LVDD has stabilized sufficiently, IOSCWT[1:0] can be set to 0x3 to reduce
the oscillation stabilization wait time.
IOSC clock system supply wait time
≤ IOSC oscillation start time (max.) + IOSC oscillation stabilization
wait time
System Clock Switching
7.4
The figure below shows the system clock selector.
fIOSC
fOSC3
fOSC1
S1C17564
CLKSRC[1:0]
System clock
4.1 System Clock Selector
Figure 7.
The S1C17554 has two system clock sources (OSC3 and OSC1) and the S1C17564 has three system clock sources
(IOSC, OSC3, and OSC1). The system clock can be switched using CLKSRC[1:0]/CLG_SRC register. After an
initial reset, the S1C17554 starts operating using OSC3 as the system clock and the S1C17564 starts operating us-
ing IOSC. When no high-speed processing is required, switch the system clock to OSC1 and stop the high-speed
oscillator circuit to reduce current consumption.
4.1 System Clock Selection
Table 7.
CLKSRC[1:0]
System clock source
S1C17554
S1C17564
0x3
Reserved
0x2
OSC3 (default)
OSC3
0x1
OSC1
0x0
Reserved
IOSC (default)
The following shows system clock switching procedures:
Switching the system clock to OSC3 from IOSC or OSC1
1. Set the OSC3 oscillation stabilization wait time if necessary. (OSC3WT[1:0])
2. Disable the OSC3 oscillation stabilization wait circuit when a stabilized external clock is input to the OSC3
pin. (OSC3WCE = 0)
3. Turn the OSC3 oscillator on if it is off. (OSC3EN = 1)
4. Select the OSC3 clock as the system clock. (CLKSRC[1:0] = 0x2)
5. Turn the IOSC or OSC1 oscillator off if peripheral modules and FOUTA/B output circuits have not used the
IOSC or OSC1 clock.