8 I/O PORTS (P)
S1C17554/564 TECHNICAL MANUAL
Seiko Epson Corporation
8-11
D[7:2]
Reserved
D[1:0]
P0KRST[1:0]: P0 Port Key-Entry Reset Configuration Bits
Selects the port combination used for P0 port key-entry reset.
8.3 P0 Port Key-Entry Reset Settings
Table 8.
P0KRST[1:0]
Ports used for resetting
0x3
P00, P01, P02, P03
0x2
P00, P01, P02
0x1
P00, P01
0x0
Not used
(Default: 0x0)
The key-entry reset function performs an initial reset by inputting Low level simultaneously to the ports
selected here. For example, if P0KRST[1:0] is set to 0x3, an initial reset is performed when the four
ports P00 to P03 are simultaneously set to Low level.
Set P0KRST[1:0] to 0x0 when this reset function is not used.
Note: The P0 port key-entry reset function is disabled at initial reset and cannot be used for power-
on reset.
Px Port Input Enable Registers (Px_IEN)
Register name Address
Bit
Name
Function
Setting
Init. R/W
Remarks
Px Port Input
Enable Register
(Px_IEN)
0x520a
0x521a
0x522a
0x523a
0x524a
(8 bits)
D7–0 PxIEN[7:0] Px[7:0] port input enable
1 Enable
0 Disable
1
(0xff)
R/W
Note: P0IEN[3:0] only are available for the P0 ports. PxIEN[5:0] only are available for the P4 and P5
ports. Other bits are reserved and always read as 0.
D[7:0]
PxIEN[7:0]: Px[7:0] Port Input Enable Bits
Enables or disables port inputs.
1 (R/W): Enable (default)
0 (R/W): disable
PxIENy is the input enable bit that corresponds directly to the Pxy port. Setting to 1 enables input and
the corresponding port pin input or output signal level can be read out from the Px_IN register. Setting
to 0 disables input.
Refer to Table 8.3.1 for more information on port input/output status, including settings other than for
the Px_IEN register.
P0[3:0] Port Function Select Register (P00_03PMUX)
Register name Address
Bit
Name
Function
Setting
Init. R/W
Remarks
P0[3:0] Port
Function Select
Register
(P00_03PMUX)
0x52a0
(8 bits)
D7–6 P03MUX[1:0] P03 port function select
P03MUX[1:0]
Function
0x0 R/W
* S1C17564 only
0x3
0x2
0x1
0x0
reserved
US_SSI1*
AIN3
P03
D5–4 P02MUX[1:0] P02 port function select
P02MUX[1:0]
Function
0x0 R/W
0x3
0x2
0x1
0x0
reserved
US_SSI0*
AIN2
P02
D3–2 P01MUX[1:0] P01 port function select
P01MUX[1:0]
Function
0x0 R/W
0x3
0x2
0x1
0x0
reserved
AIN1
P01
D1–0 P00MUX[1:0] P00 port function select
P00MUX[1:0]
Function
0x0 R/W
0x3
0x2
0x1
0x0
reserved
AIN0
P00