15 UART
15-2
Seiko Epson Corporation
S1C17554/564 TECHNICAL MANUAL
UART Input/Output Pins
15.2
Table 15.2.1 lists the UART input/output pins.
2.1 List of UART Pins
Table 15.
Pin name
I/O
Qty
Function
SIN0 (Ch.0)
SIN1 (Ch.1)
I
2
UART Ch.x data input pin
Inputs serial data sent from an external serial device.
SOUT0 (Ch.0)
SOUT1 (Ch.1)
O
2
UART Ch.x data output pin
Outputs serial data sent to an external serial device.
SCLK0 (Ch.0)
SCLK1 (Ch.1)
I
2
UART Ch.x clock input pin
Inputs the transfer clock when an external clock is used.
The UART input/output pins (SINx, SOUTx, SCLKx) are shared with I/O ports and are initially set as general pur-
pose I/O port pins. The pin functions must be switched using the port function select bits to use the general purpose
I/O port pins as UART input/output pins.
For detailed information on pin function switching, see the “I/O Ports (P)” chapter.
Baud Rate Generator
15.3
The UART module includes a baud rate generator to generate the transfer (sampling) clock. It consists of an 8-bit
programmable timer with fine mode. The timer counts down from the initial value set via software and outputs an
underflow signal when the counter underflows. The underflow signal is used to generate the transfer clock. The un-
derflow cycle can be programmed by selecting the clock source and initial data, enabling the application program
to obtain serial transfer rates as required. Fine mode provides a function that minimizes transfer rate errors.
S1C17564
Baud rate register
UART_BRx
Underflow
Fine mode setting
Clock enable
ct_clk
Division ratio
selection
Clock source
selection
Down counter
Control circuit
FMD[3:0]
CLKEN
CLKDIV[1:0] CLKSRC[1:0]
Baud rate generator for UART Ch.x
OSC1 clock
External clock (SCLKx)
OSC3 clock
Divider
(1/1–1/8)
IOSC clock
Divider
(1/1–1/8)
Serial transfer clock
sclk
sclk16
1/16
3.1 Baud Rate Generator
Figure 15.
Clock source settings
The clock source can be selected from IOSC (S1C17564), OSC3, OSC1, or external clock using CLKSRC[1:0]/
UART_CLKx register.
3.1 Clock Source Selection
Table 15.
CLKSRC[1:0]
Clock source
0x3
External clock (SCLKx)
0x2
OSC3
0x1
OSC1
0x0
IOSC (S1C17564)
(Default: 0x0)
Note: When inputting the external clock via the SCLKx pin, the clock duty ratio must be 50%.
When IOSC or OSC3 is selected as the clock source, use CLKDIV[1:0]/UART_CLKx register to select the di-
vision ratio.